Manuale UtenteSommarioChapter 1 Introduction61.1 Block Diagram6Figure 1.1 LAN9500/LAN9500i System Diagram61.1.1 Overview61.1.2 USB71.1.3 FIFO Controller71.1.4 Ethernet71.1.5 Power Management71.1.6 EEPROM Controller81.1.7 General Purpose I/O8Chapter 2 Pin Description and Configuration9Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW)9Table 2.1 MII Interface Pins10Table 2.2 EEPROM Pins13Table 2.3 JTAG Pins13Table 2.4 Miscellaneous Pins14Table 2.5 USB Pins16Table 2.6 Ethernet PHY Pins16Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad17Table 2.8 No-Connect Pins17Table 2.9 56-QFN Package Pin Assignments182.1 Buffer Types19Table 2.10 Buffer Types19Chapter 3 EEPROM Controller (EPC)203.1 EEPROM Format20Table 3.1 EEPROM Format20Table 3.2 Configuration Flags Description213.2 EEPROM Defaults22Table 3.3 EEPROM Defaults223.3 EEPROM Auto-Load223.4 An Example of EEPROM Format Interpretation23Table 3.4 Dump of EEPROM Memory23Table 3.5 EEPROM Example - 256 Byte EEPROM24Chapter 4 Operational Characteristics284.1 Absolute Maximum Ratings*284.2 Operating Conditions**284.3 Power Consumption294.3.1 SUSPEND029Table 4.1 SUSPEND0 - Supply and Current @3.3V294.3.2 SUSPEND129Table 4.2 SUSPEND1 - Supply and Current @3.3V294.3.3 SUSPEND229Table 4.3 SUSPEND2 - Supply and Current @3.3V294.3.4 Operational Power Consumption30Table 4.4 Operational Power Consumption - Supply and Current @3.3V304.3.5 Customer Evaluation Board Operational Power Consumption30Table 4.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V304.4 DC Specifications31Table 4.6 I/O Buffer Characteristics31Table 4.7 100BASE-TX Transceiver Characteristics32Table 4.8 10BASE-T Transceiver Characteristics324.5 AC Specifications334.5.1 Equivalent Test Load33Figure 4.1 Output Equivalent Test Load334.5.2 Power-On Configuration Strap Valid Timing34Figure 4.2 Power-On Configuration Strap Valid Timing34Table 4.9 Power-On Configuration Strap Valid Timing344.5.3 Reset and Configuration Strap Timing35Figure 4.3 nRESET Reset Pin Timing35Table 4.10 nRESET Reset Pin Timing Values354.5.4 EEPROM Timing36Figure 4.4 EEPROM Timing36Table 4.11 EEPROM Timing Values364.5.5 Turbo MII Interface Timing37Figure 4.1 Turbo MII Output Timing37Table 4.12 Turbo MII Output Timing Values37Figure 4.2 Turbo MII Input Timing37Table 4.13 Turbo MII Interface Timing Values384.6 Clock Circuit39Table 4.14 LAN9500/LAN9500i Crystal Specifications39Chapter 5 Package Outline40Figure 5.1 LAN9500/LAN9500i 56-QFN Package40Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions40Figure 5.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern41Chapter 6 Revision History42Table 6.1 Customer Revision History42Dimensioni: 697 KBPagine: 43Language: EnglishApri il manuale
Manuale UtenteSommarioChapter 1 Introduction61.1 Block Diagram6Figure 1.1 LAN9500/LAN9500i System Diagram61.1.1 Overview61.1.2 USB71.1.3 FIFO Controller71.1.4 Ethernet71.1.5 Power Management71.1.6 EEPROM Controller81.1.7 General Purpose I/O8Chapter 2 Pin Description and Configuration9Figure 2.1 LAN9500/LAN9500i 56-QFN Pin Assignments (TOP VIEW)9Table 2.1 MII Interface Pins10Table 2.2 EEPROM Pins13Table 2.3 JTAG Pins13Table 2.4 Miscellaneous Pins14Table 2.5 USB Pins16Table 2.6 Ethernet PHY Pins16Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad17Table 2.8 No-Connect Pins17Table 2.9 56-QFN Package Pin Assignments182.1 Buffer Types19Table 2.10 Buffer Types19Chapter 3 EEPROM Controller (EPC)203.1 EEPROM Format20Table 3.1 EEPROM Format20Table 3.2 Configuration Flags Description213.2 EEPROM Defaults22Table 3.3 EEPROM Defaults223.3 EEPROM Auto-Load223.4 An Example of EEPROM Format Interpretation23Table 3.4 Dump of EEPROM Memory23Table 3.5 EEPROM Example - 256 Byte EEPROM24Chapter 4 Operational Characteristics284.1 Absolute Maximum Ratings*284.2 Operating Conditions**284.3 Power Consumption294.3.1 SUSPEND029Table 4.1 SUSPEND0 - Supply and Current @3.3V294.3.2 SUSPEND129Table 4.2 SUSPEND1 - Supply and Current @3.3V294.3.3 SUSPEND229Table 4.3 SUSPEND2 - Supply and Current @3.3V294.3.4 Operational Power Consumption30Table 4.4 Operational Power Consumption - Supply and Current @3.3V304.3.5 Customer Evaluation Board Operational Power Consumption30Table 4.5 Customer Evaluation Board Operational Power Consumption - Supply and Current @3.3V304.4 DC Specifications31Table 4.6 I/O Buffer Characteristics31Table 4.7 100BASE-TX Transceiver Characteristics32Table 4.8 10BASE-T Transceiver Characteristics324.5 AC Specifications334.5.1 Equivalent Test Load33Figure 4.1 Output Equivalent Test Load334.5.2 Power-On Configuration Strap Valid Timing34Figure 4.2 Power-On Configuration Strap Valid Timing34Table 4.9 Power-On Configuration Strap Valid Timing344.5.3 Reset and Configuration Strap Timing35Figure 4.3 nRESET Reset Pin Timing35Table 4.10 nRESET Reset Pin Timing Values354.5.4 EEPROM Timing36Figure 4.4 EEPROM Timing36Table 4.11 EEPROM Timing Values364.5.5 Turbo MII Interface Timing37Figure 4.1 Turbo MII Output Timing37Table 4.12 Turbo MII Output Timing Values37Figure 4.2 Turbo MII Input Timing37Table 4.13 Turbo MII Interface Timing Values384.6 Clock Circuit39Table 4.14 LAN9500/LAN9500i Crystal Specifications39Chapter 5 Package Outline40Figure 5.1 LAN9500/LAN9500i 56-QFN Package40Table 5.1 LAN9500/LAN9500i 56-QFN Dimensions40Figure 5.2 LAN9500/LAN9500i 56-QFN Recommended PCB Land Pattern41Chapter 6 Revision History42Table 6.1 Customer Revision History42Dimensioni: 697 KBPagine: 43Language: EnglishApri il manuale
