Intel SL2YM ユーザーズマニュアル
Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
38
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. This is the Pentium II processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute voltage
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute voltage
the BCLK signal may dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This guideline is an
absolute value.
4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The midpoint
voltage level of this ledge should be within the range of the guideline.
5. The ledge (V7’) is allowed to have peak-to-peak oscillation as given in the guideline.
3.2
AGTL+ Signal Quality Specifications and Measurement
Guidelines
Guidelines
Many scenarios have been simulated to generate a set of GTL+ layout guidelines which are
available in AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium
available in AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium
®
II Processor and Intel
®
440BX AGPset (Order Number 243735). Refer to the Pentium
®
II Processor Developer's Manual
(Order Number 243502) for the GTL+ buffer specification.
Table 22. BCLK Signal Quality Guidelines for Edge Finger Measurement
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1’: BCLK V
IL
0.5
V
14
V2’: BCLK V
IH
2.0
V
14
V3’: V
IN
Absolute Voltage Range
–0.5
3.3
V
14
2
V4’: Rising Edge Ringback
2.0
V
14
3
V5’: Falling Edge Ringback
0.5
V
14
3
V6’: T
line
Ledge Voltage
1.0
1.7
V
14
At Ledge Midpoint
4
V7’: T
line
Ledge Oscillation
0.2
V
14
Peak-to-Peak
5
Figure 14. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
000808
T3
V3
V5
V3
V2
V1
V7
V6
T6
T4
T5
V4
Tim e
Vo
lt
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