Freescale Semiconductor 56F8322 ユーザーズマニュアル
Serial Peripheral Interface (SPI) Timing
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
115
Preliminary
10.9 Serial Peripheral Interface (SPI) Timing
Table 10-18 SPI Timing
1
1. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
Master
Slave
t
C
50
50
50
—
—
—
ns
ns
ns
,
Enable lead time
Master
Slave
Master
Slave
t
ELD
—
25
—
—
—
ns
ns
ns
Enable lag time
Master
Slave
Master
Slave
t
ELG
—
100
—
—
—
ns
ns
ns
Clock (SCK) high time
Master
Slave
Master
Slave
t
CH
17.6
25
—
—
—
ns
ns
ns
,
Clock (SCK) low time
Master
Slave
Master
Slave
t
CL
16
16.67
—
—
—
ns
ns
ns
Data set up time required for inputs
Master
Slave
Master
Slave
t
DS
20
0
—
—
—
ns
ns
ns
,
Data hold time required for inputs
Master
Slave
Master
Slave
t
DH
0
2
2
—
—
—
ns
ns
ns
,
Access time (time to data active from high-impedance
state)
Slave
state)
Slave
t
A
4.8
15
ns
Disable time (hold time to high-impedance state)
Slave
Slave
t
D
3.7
15.2
ns
Data Valid for outputs
Master
Slave (after enable edge)
Master
Slave (after enable edge)
t
DV
—
—
—
4.5
20.4
ns
ns
ns
,
Data invalid
Master
Slave
Master
Slave
t
DI
0
0
0
—
—
—
ns
ns
ns
,
Rise time
Master
Slave
Master
Slave
t
R
—
—
—
11.5
10.0
10.0
ns
ns
ns
,
Fall time
Master
Slave
Master
Slave
t
F
—
—
—
9.7
9.0
9.0
ns
ns
ns
,