Freescale Semiconductor 56F8322 ユーザーズマニュアル
56F8322 Techncial Data, Rev. 10.0
118
Freescale Semiconductor
Preliminary
10.10 Quad Timer Timing
Figure 10-13 Timer Timing
10.11 Quadrature Decoder Timing
Note: The Quadrature Decoder is NOT available in the 56F8122 device.
Table 10-19 Timer Timing
1, 2
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
Timer input period
P
IN
2T + 6
—
ns
Timer input high / low period
P
INHL
1T + 3
—
ns
Timer output period
P
OUT
1T - 3
—
ns
Timer output high / low period
P
OUTHL
0.5T - 3
—
ns
Table 10-20 Quadrature Decoder Timing
1, 2
1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
Quadrature input period
P
IN
4T + 12
—
ns
Quadrature input high / low period
P
HL
2T + 6
—
ns
Quadrature phase period
P
PH
1T + 3
—
ns
P
OUT
P
OUTHL
P
OUTHL
P
IN
P
INHL
P
INHL
Timer Inputs
Timer Outputs