Freescale Semiconductor 56F8322 ユーザーズマニュアル
56F8322 Techncial Data, Rev. 10.0
58
Freescale Semiconductor
Preliminary
5.6.2.1
Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2.2
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
It is disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 1
•
10 = IRQ is priority level 2
•
11 = IRQ is priority level 3
5.6.2.3
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
It is disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 1
•
10 = IRQ is priority level 2
•
11 = IRQ is priority level 3
5.6.2.4
EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—
Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
It is disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 1
•
10 = IRQ is priority level 2
•
11 = IRQ is priority level 3
5.6.3
Interrupt Priority Register 2 (IPR2)
Figure 5-5 Interrupt Priority Register 2 (IPR2)
Base + $2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FMCBE IPL
FMCC IPL
FMERR IPL
LOCK IPL
LVI IPL
0
0
0
0
IRQA IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0