Freescale Semiconductor 56F8322 ユーザーズマニュアル
Register Descriptions
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
89
Preliminary
6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—Bit 5
Each bit controls clocks to the indicated peripheral.
•
1 = Clocks are enabled
•
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11 Serial Communications Interface 0 Enable (SCI0)—Bit 4
Each bit controls clocks to the indicated peripheral.
•
1 = Clocks are enabled
•
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
Each bit controls clocks to the indicated peripheral.
•
1 = Clocks are enabled
•
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.13 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
1 = Clocks are enabled
•
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.14 Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
6.5.9.15 Pulse Width Modulator A Enable (PWMA)—Bit 0
Each bit controls clocks to the indicated peripheral.
•
1 = Clocks are enabled
•
0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.10
I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in
Note:
If this register is set to something other than the top of memory (EOnCE register space) and the EX bit
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.