Motorola CPCI-6020 ユーザーズマニュアル

To enable Flash Bank A, place a jumper across pins 1 and 2 of header J24. To enable Flash 
Bank B, place a jumper across pins 2 and 3 of header J24.

A 2 mm, 8-pin low profile header located on side 1 of the CPCI-6020 provides the means to 
change some of the Harrier power up configuration settings. The pin assignments for this 
header, along with the power up setting with the jumper on or off, are as follows (boards are 
shipped with all jumpers off):

This 0.1 inch, 2-pin header (J21)  located on the CPCI-6020 is used to disable 66 MHz 
operation on PCI Bus B. When a jumper is installed between pins 1 and 2, PCI Bus B will 
operate at 33 MHz regardless of whether the PMC is capable of 66 MHz. This prevents the 
secondary Ethernet controller from being disabled if a 66 MHz capable PMC is installed. The 
jumper pulls the M66EN signal low so the PMC can be aware that the bus is operating at 33 
MHz.

This 0.1 inch, 2-pin header (J18) located on the CPCI-6020 is used to disable +/-12 V on the 
board.  

1-2

Flash Bank A Enabled (32 MB, soldered)

2-3

Flash Bank B Enabled (1 MB, sockets)

Factory Configuration

1-2

PUST0 = 0
Harrier PUST Bit 0 in GCSR Register

PUST0 = 1

3-4

PUST1 = 0
Harrier PUST Bit 1 in GCSR Register

PUST1 = 1

5-6

PUST2 = 0
Harrier PUST Bit 2 in GCSR Register

PUST2 = 1

7-8

PUST3 = 0
Harrier PUST Bit 2 in GCSR Register

PUST3 = 1

GND

M66EN