Motorola CPCI-6020 ユーザーズマニュアル
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CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
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Functional Description
4.1
Overview
The CPCI-6020 is a CompactPCI system slot controller based on the PowerPlus III architecture
and includes support for the Motorola High Availability (HA) architecture (such as the
CPX8216). It consists of the MPC7410 processor and L2 backside cache, dual Harrier System
Memory Controller /PCI Host Bridge ASICs, 32 MB plus1 MB of flash memory, and 128 MB to
2 GB of ECC-protected SDRAM on mezzanines. Front panel access is provided for one of the
two 10 BaseT/100 Base TX Ethernet channels, an RS-232 serial debug port, two USB ports
and the single PMC slot.
and includes support for the Motorola High Availability (HA) architecture (such as the
CPX8216). It consists of the MPC7410 processor and L2 backside cache, dual Harrier System
Memory Controller /PCI Host Bridge ASICs, 32 MB plus1 MB of flash memory, and 128 MB to
2 GB of ECC-protected SDRAM on mezzanines. Front panel access is provided for one of the
two 10 BaseT/100 Base TX Ethernet channels, an RS-232 serial debug port, two USB ports
and the single PMC slot.
The front Ethernet port may also be routed (by means of custom-build option) to the backplane
via the CompactPCI J3 and J5 connectors. Other I/O routed to the backplane include a second
Ethernet port, two 16550 compatible asynchronous serial ports, two high speed synchronous
serial ports, and IDE. A CompactFlash Type I/II compatible socket residing on the IDE Bus is
included onboard.
via the CompactPCI J3 and J5 connectors. Other I/O routed to the backplane include a second
Ethernet port, two 16550 compatible asynchronous serial ports, two high speed synchronous
serial ports, and IDE. A CompactFlash Type I/II compatible socket residing on the IDE Bus is
included onboard.
The floppy disk controller, keyboard, and mouse are supported only on the CPCI-6060 5E
variants. A parallel port, which was available on the previous generation board, has been
eliminated in favor of routing the Ethernet ports to the backplane connectors.
variants. A parallel port, which was available on the previous generation board, has been
eliminated in favor of routing the Ethernet ports to the backplane connectors.
The CPCI-6020 features two host bridges, which allow two totally independent PCI Bus
hierarchies. One bus supports the single PMC and the secondary Ethernet port. This bus may
be run at 33 MHz or 66 MHz depending on the capability of the installed PMC. When run at 66
MHz, the secondary Ethernet is disabled because it is not 66 MHz capable. The other PCI Bus
supports all other onboard PCI resources and runs at a fixed speed of 33 MHz.
hierarchies. One bus supports the single PMC and the secondary Ethernet port. This bus may
be run at 33 MHz or 66 MHz depending on the capability of the installed PMC. When run at 66
MHz, the secondary Ethernet is disabled because it is not 66 MHz capable. The other PCI Bus
supports all other onboard PCI resources and runs at a fixed speed of 33 MHz.
The CPCI-6020 board has a 190-pin Mictor connector attached to the processor bus to support
board debug. There is also access provided to the MPC7410 processor JTAG port via a
standard 16 pin header.
board debug. There is also access provided to the MPC7410 processor JTAG port via a
standard 16 pin header.