Motorola CPCI-6020 ユーザーズマニュアル
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)
Functional Description
Secondary Ethernet Channel
86
The Harrier PCI I/O buffers operate at +3.3 V output levels and are +5 V tolerant allowing the
PCI interface to operate at either voltage level. VIO is connected to +3.3 V on the planned
standard product, but may be connected to +5 V by means of a build option. If VIO is connected
to +5 V then 66 MHz PCI operation is prohibited and disabled by means of a build option.
PCI interface to operate at either voltage level. VIO is connected to +3.3 V on the planned
standard product, but may be connected to +5 V by means of a build option. If VIO is connected
to +5 V then 66 MHz PCI operation is prohibited and disabled by means of a build option.
The following special function processor PMC pins, as defined by the Processor PMC Standard
VITA 32-2003, are implemented on the CPCI-6020 as described in the following table:
VITA 32-2003, are implemented on the CPCI-6020 as described in the following table:
4.4.2
Secondary Ethernet Channel
The CPCI-6020 uses the Intel GD82551IT Ethernet controller to implement a secondary
10BaseT/100 BaseTx Ethernet channel on PCI Bus B. The GD82551IT consists of both the
Media Access Controller (MAC) and the physical layer (PHY) in a single integrated package.
The secondary Ethernet provides only rear I/O by routing the Ethernet transmit and receive
signal pairs to J5 connector.
10BaseT/100 BaseTx Ethernet channel on PCI Bus B. The GD82551IT consists of both the
Media Access Controller (MAC) and the physical layer (PHY) in a single integrated package.
The secondary Ethernet provides only rear I/O by routing the Ethernet transmit and receive
signal pairs to J5 connector.
The GD82551IT82551IT is limited to a maximum of 33 MHz PCI Bus operation. If the PMC slot
is populated with a 66 MHz capable PMC, the PCI Bus B will run at 66 MHz and this Ethernet
controller will be disabled by keeping it in reset.
is populated with a 66 MHz capable PMC, the PCI Bus B will run at 66 MHz and this Ethernet
controller will be disabled by keeping it in reset.
The 82551IT interfaces to an AT93C46 serial EEPROM device which provides power up
configuration information for the 82551IT. This is a 1 kilobit device organized as 64, 16-bit
words.
configuration information for the 82551IT. This is a 1 kilobit device organized as 64, 16-bit
words.
Table 4-1 Special Function Processor PMC Pins
PrPMC Signal
Pin Number
Support
PRESENT#
J11-7
The PRESENT# signal from the slot is used in conjunction with
M66EN to detect the presence of a 66 MHz capable PMC. The state
of this bit is readable in the external register set on Harrier A Xport
channel 2.
M66EN to detect the presence of a 66 MHz capable PMC. The state
of this bit is readable in the external register set on Harrier A Xport
channel 2.
MONARCH#
J12-64
The CPCI-6020 leaves the MONARCH# pin floating, causing any
installed processor PMC to operate as a slave module. Processor
PMC monarch mode is not supported.
installed processor PMC to operate as a slave module. Processor
PMC monarch mode is not supported.
IDSELB
J12-34
IDSELB is connected to PCI Bus B AD[17].
REQB#
J12-52
REQB# is routed to the PCI Bus B arbiter.
GNTB#
J12-54
GNTB# is routed to the PCI Bus B arbiter.
M66EN
J12-47
The CPCI-6020 has a weak pull-up on this signal. If the signal is
grounded, as it will be on 33 MHz PMCs, the PCI Bus B will be
configured to run at 33 MHz upon power-up. If this line is left floating,
as it will be on 66 MHz capable PMCs, and it is qualified by assertion
of PRESENT#, then PCI Bus B will be configured to run at 66 MHz
upon power-up (as a side effect the secondary ethernet controller
on PCI Bus B will be disabled). A jumper is provided on the CPCI-
6020 to ground and thereby defeat the 66 MHz enable signal.
grounded, as it will be on 33 MHz PMCs, the PCI Bus B will be
configured to run at 33 MHz upon power-up. If this line is left floating,
as it will be on 66 MHz capable PMCs, and it is qualified by assertion
of PRESENT#, then PCI Bus B will be configured to run at 66 MHz
upon power-up (as a side effect the secondary ethernet controller
on PCI Bus B will be disabled). A jumper is provided on the CPCI-
6020 to ground and thereby defeat the 66 MHz enable signal.
RESETOUT_L
J12-60
The CPCI-6020 does not make any connection to RESETOUT_L.
EREADY
J12-58
The EREADY signal (driven by the PMC) is connected to the Harrier
B EREADY pin and may be read in the XCSR.MCSR.EREADY
register of Harrier B. A pull-up is provided on board.
B EREADY pin and may be read in the XCSR.MCSR.EREADY
register of Harrier B. A pull-up is provided on board.