Motorola MC68340 ユーザーズマニュアル
MOTOROLA
MC68340 USER’S MANUAL
3- 7
OP1
OP0
OP0
OP2
OP1
OP0
OP1
OP0
OP3
OP2
OP1
OP0
OP2
OP1
OP0
31
23
15
7
0
D0
D8
D15
D7
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
(OP0)
OP0
(OP1)
OP1
OP0
(OP1)
OP0
OP1
A0
SIZ0
SIZ1
Case
(a)
(b)
(c)
(d)
(e)
(b)
(c)
(d)
(e)
(f)
(g)
0
1
X
1
0
0
1
0
0
X
0
1
1
0
X
1
0
0
1
0
1
0
0
0
X
0
0
0
1
0
0
0
0
0
X
Transfer Case
Byte to Byte
Byte to Word (Even)
Byte to Word (Odd)
Word to Byte (Aligned)
Word to Word (Aligned)
Long Word to Byte (Aligned)
Long Word to Word (Aligned)
Byte to Word (Even)
Byte to Word (Odd)
Word to Byte (Aligned)
Word to Word (Aligned)
Long Word to Byte (Aligned)
Long Word to Word (Aligned)
OPERAND
Data Bus
DSACK0
DSACK1
NOTES:
1. Operands in parentheses are ignored by the MC68340 during read cycles.
1. Operands in parentheses are ignored by the MC68340 during read cycles.
2. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer.
Figure 3-2. MC68340 Interface to Various Port Sizes
3.2.2 Misaligned Operands
In this architecture, the basic operand size is 16 bits. Operand misalignment refers to
whether an operand is aligned on a word boundary or overlaps the word boundary,
determined by address line A0. When A0 is low, the address is even and is a word and
byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte
operand is properly aligned at any address; a word or long-word operand is misaligned at
an odd address.
whether an operand is aligned on a word boundary or overlaps the word boundary,
determined by address line A0. When A0 is low, the address is even and is a word and
byte boundary. When A0 is high, the address is odd and is a byte boundary only. A byte
operand is properly aligned at any address; a word or long-word operand is misaligned at
an odd address.
At most, each bus cycle can transfer a word of data aligned on a word boundary. If the
MC68340 transfers a long-word operand over a 16-bit port, the most significant operand
word is transferred on the first bus cycle, and the least significant operand word is
transferred on a following bus cycle.
MC68340 transfers a long-word operand over a 16-bit port, the most significant operand
word is transferred on the first bus cycle, and the least significant operand word is
transferred on a following bus cycle.
The CPU32 restricts all operands (both data and instructions) to be aligned. That is, word
and long-word operands must be located on a word or long-word boundary, respectively.
The only type of transfer that can be performed to an odd address is a single-byte
transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the
CPU32 generates an address error exception, and enters exception processing. Refer to
Section 5 CPU32 for more information on exception processing.
and long-word operands must be located on a word or long-word boundary, respectively.
The only type of transfer that can be performed to an odd address is a single-byte
transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the
CPU32 generates an address error exception, and enters exception processing. Refer to
Section 5 CPU32 for more information on exception processing.
3.2.3 Operand Transfer Cases
The following cases are examples of the allowable alignments of operands to ports.
3.2.3.1 BYTE OPERAND TO 8-BIT PORT, ODD OR EVEN (A0 = X). The MC68340
drives the address bus with the desired address and the SIZx pins to indicate a single-
byte operand.
drives the address bus with the desired address and the SIZx pins to indicate a single-
byte operand.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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