Motorola MC68340 ユーザーズマニュアル
3- 32
MC68340 USER’S MANUAL
MOTOROLA
3.5 BUS EXCEPTION CONTROL CYCLES
The bus architecture requires assertion of
DSACK
≈
from an external device to signal that
a bus cycle is complete. Neither
DSACK
≈
nor
AVEC
is asserted in the following cases:
•
DSACK
≈
/
AVEC
is programmed to respond internally.
• The external device does not respond.
• Various other application-dependent errors occur.
The MC68340 provides
BERR
when no device responds by asserting
DSACK
≈
/
AVEC
within an appropriate period of time after the MC68340 asserts
AS
. This mechanism
allows the cycle to terminate and the MC68340 to enter exception processing for the error
condition.
condition.
HALT
is also used for bus exception control. This signal can be asserted by an
external device for debugging purposes to cause single bus cycle operation, or, in
combination with
combination with
BERR
, a retry of a bus cycle in error. To properly control termination of a
bus cycle for a retry or a bus error condition,
DSACK
≈
,
BERR
, and
HALT
can be asserted
and negated with the rising edge of the MC68340 clock. This assures that when two
signals are asserted simultaneously, the required setup and hold time for both is met for
the same falling edge of the MC68340 clock. This or an equivalent precaution should be
designed into the external circuitry to provide these signals. Alternatively, the internal bus
monitor could be used. The acceptable bus cycle terminations for asynchronous cycles
are summarized in relation to
signals are asserted simultaneously, the required setup and hold time for both is met for
the same falling edge of the MC68340 clock. This or an equivalent precaution should be
designed into the external circuitry to provide these signals. Alternatively, the internal bus
monitor could be used. The acceptable bus cycle terminations for asynchronous cycles
are summarized in relation to
DSACK
≈
assertion as follows (case numbers refer to Table
3-4):
• Normal Termination:
DSACK
≈
is asserted;
BERR
and
HALT
remain negated (case 1).
• Halt Termination:
HALT
is asserted at the same time as or before
DSACKx
, and
BERR
remains negated (case 2).
• Bus Error Termination:
BERR
is asserted in lieu of, at the same time as, or before
DSACK
≈
(case 3) or after
DSACK
≈
(case 4), and
HALT
remains negated;
BERR
is
negated at the same time as or after
DSACK
≈
.
• Retry Termination:
HALT
and
BERR
are asserted in lieu of, at the same time as, or
before
DSACK
≈
(case 5) or after
DSACK
≈
(case 6);
BERR
is negated at the same
time as or after
DSACK
≈
, and
HALT
may be negated at the same time as or after
BERR
.
Table 3-4 lists various combinations of control signal sequences and the resulting bus
cycle terminations. To ensure predictable operation,
cycle terminations. To ensure predictable operation,
BERR
and
HALT
should be negated
according to the specifications given in Section 11 Electrical Characteristics.
DSACK
≈
BERR
, and
HALT
may be negated after
AS
. If
DSACK
≈
or
BERR
remain asserted into S2
of the next bus cycle, that cycle may be terminated prematurely.
EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated
address space. The timer asserts
address space. The timer asserts
BERR
after timeout (case 3).
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..