Fujitsu CM71-00101-5E ユーザーズマニュアル
92
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.18
OR (Or Word Data of Source Register to Destination
Register)
Register)
Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the
results to "Ri".
results to "Ri".
■
OR (Or Word Data of Source Register to Destination Register)
Assembler format:
OR Rj, Ri
Operation:
Ri or Rj
→
Ri
Flag change:
N:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z:
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
1 cycle
Instruction format:
Example:
OR R2, R3
N
Z
V
C
C
C
–
–
MSB
LSB
1
0
0
1
0
0
1
0
Rj
Ri
R2
R3
1 1 1 1
0 0 0 0
1 0 1 0
1 0 1 0
N Z V C
CCR
R2
R3
CCR
0 0 0 0
N Z V C
0 0 0 0
1 1 1 1
1 0 1 0
1 1 1 1
0 0 0 0
Before execution
After execution
Instruction bit pattern : 1001 0010 0010 0011