Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 データシート
製品コード
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
74
Datasheet
5.1.14
DEVEN—Device Enable
B/D/F/Type:
0/0/0/PCI
Address Offset: 54–57h
Default Value:
000023DBh
Access:
RO, RW/L
Size:
32 bits
Allows for enabling/disabling of PCI devices and functions that are within the MCH. The
table below the bit definitions describes the behavior of all combinations of transactions
to devices controlled by this register. All the bits in this register are Intel TXT Lockable.
Bit
Access
Default
Value
Description
31:14
RO
00000h
Reserved
13
RW/L
1b
PE1 Enable (D6EN):
0 = Bus 0, Device 6 is disabled and hidden.
1 = Bus 1, Device 6 is enabled and visible.
0 = Bus 0, Device 6 is disabled and hidden.
1 = Bus 1, Device 6 is enabled and visible.
NOTE: This bit description only applies to the 3210 MCH in dual x8 mode. For
the 3200 MCH, this bit is reserved.
12:11
RO
00b
Reserved
9
RW/L
1b
EP Function 3 (D3F3EN):
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 3 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1),
then Device 3, Function 3 is disabled and hidden independent of the state of this
bit.
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 3 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1),
then Device 3, Function 3 is disabled and hidden independent of the state of this
bit.
8
RW/L
1b
EP Function 2 (D3F2EN):
0 = Bus 0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 2 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1),
then Device 3, Function 2 is disabled and hidden independent of the state of this
bit.
0 = Bus 0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 2 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1 or CAPID0[56] = 1),
then Device 3, Function 2 is disabled and hidden independent of the state of this
bit.
7
RW/L
1b
EP Function 1 (D3F1EN):
0 = Bus 0, Device 3, Function 1 is disabled and hidden
1 = Bus 0, Device 3, Function 1 is enabled and visible.
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 1 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1), then Device 3,
Function 1 is disabled and hidden independent of the state of this bit.
0 = Bus 0, Device 3, Function 1 is disabled and hidden
1 = Bus 0, Device 3, Function 1 is enabled and visible.
If Device 3 Function 0 is disabled and hidden, then Device 3 Function 1 is also
disabled and hidden independent of the state of this bit.
If this MCH does not have ME capability (CAPID0[57] = 1), then Device 3,
Function 1 is disabled and hidden independent of the state of this bit.
6
RW/L
1b
EP Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible.
If this MCH does not have ME capability (CAPID0[57] = 1), then Device 3,
Function 0 is disabled and hidden independent of the state of this bit.
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible.
If this MCH does not have ME capability (CAPID0[57] = 1), then Device 3,
Function 0 is disabled and hidden independent of the state of this bit.