Intel Xeon 7130N LF80550KF0878M データシート
製品コード
LF80550KF0878M
Dual-Core Intel
®
Xeon
®
Processor 7000 Series Datasheet
15
2
Electrical Specifications
2.1
Front Side Bus and GTLREF
Most Dual-Core Intel Xeon processor 7000 series FSB signals use Assisted Gunning Transceiver
Logic (AGTL+) signaling technology. The termination voltage level for the Dual-Core Intel Xeon
processor 7000 series AGTL+ signals is V
Logic (AGTL+) signaling technology. The termination voltage level for the Dual-Core Intel Xeon
processor 7000 series AGTL+ signals is V
TT
.
Termination resistors are provided on the processor silicon and are terminated to V
TT
. Intel chipsets
also provide on-die termination, thus eliminating the need to terminate the bus on the system board
for most AGTL+ signals. Some AGTL+ signals do not include on-die termination and must be
terminated on the system board.
for most AGTL+ signals. Some AGTL+ signals do not include on-die termination and must be
terminated on the system board.
When designing a system, Intel strongly recommends that design teams perform analog
simulations of the FSB. Design guidelines for the Dual-Core Intel Xeon processor 7000 series FSB
are detailed in the appropriate platform design guide.
simulations of the FSB. Design guidelines for the Dual-Core Intel Xeon processor 7000 series FSB
are detailed in the appropriate platform design guide.
Some Dual-Core Intel Xeon processor 7000 series signals include additional on-die resistors (R
L
)
to ensure proper noise margin and signal integrity specifications are met—see
for a list of
illustrates the active on-die termination. Signal listings are included in
and
2.1.1
Front Side Bus Clock and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous processor generations, the Dual-Core Intel Xeon processor 7000 series core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set
during manufacturing.
As in previous processor generations, the Dual-Core Intel Xeon processor 7000 series core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set
during manufacturing.
Figure 2-1. On-Die Front Side Bus Termination
End Agent
Signal
V
TT
Middle Agent
R
TT
Signal
R
L
R
TT
- On-die termination resistors for AGTL+ signals
R
L
- Additional on-die resistance implemented for proper noise margin and
signal integrity