Intel D845GVSR D845GVSRL ユーザーズマニュアル
製品コード
D845GVSRL
Intel Desktop Board D845GVSR Technical Product Specification
42
2.3 Fixed I/O Map
Table 16. I/O Map
Address (hex)
Size
Description
0000 - 00FF
256 bytes
Used by the Desktop Board D845GVSR. Refer to the
ICH4 data sheet for dynamic addressing information.
ICH4 data sheet for dynamic addressing information.
0170 - 0177
8 bytes
Secondary IDE channel
01F0 - 01F7
8 bytes
Primary IDE channel
0228 - 022F
(Note 1)
8
bytes
LPT3
0278 - 027F
(Note 1)
8
bytes
LPT2
02E8 - 02EF
(Note 1)
8
bytes
COM4
02F8 - 02FF
(Note 1)
8
bytes
COM2
0376
1 byte
Secondary IDE channel command port
0377, bits 6:0
7 bits
Secondary IDE channel status port
0378 - 037F
8 bytes
LPT1
03B0 - 03BB
12 bytes
Intel 82845GV GMCH
03C0 - 03DF
32 bytes
Intel 82845GV GMCH
03E8 - 03EF
8 bytes
COM3
03F0 - 03F5
6 bytes
Diskette channel 1
03F6
1 byte
Primary IDE channel command port
03F8 - 03FF
8 bytes
COM1
04D0 - 04D1
2 bytes
Edge/level triggered PIC
LPTn + 400
8 bytes
ECP port, LPTn base address + 400h
0CF8 - 0CFB
(Note 2)
4 bytes
PCI configuration address register
0CF9
(Note 3)
1 byte
Turbo and reset control register
0CFC - 0CFF
4 bytes
PCI configuration data register
FFA0 - FFA7
8 bytes
Primary bus master IDE registers
FFA8 - FFAF
8 bytes
Secondary bus master IDE registers
Notes:
1.
Default, but can be changed to another address range
2.
Dword access only
3.
Byte access only
✏
NOTE
Some additional I/O addresses are not available due to ICH4 address aliasing. The ICH4 data
sheet provides more information on address aliasing.
sheet provides more information on address aliasing.
For information about
Refer to
Obtaining the ICH4 data sheet