Super Talent Technology 4GB DDR3 PC3-10600 1333MHz W1333UB4GV ユーザーズマニュアル
製品コード
W1333UB4GV
240-Pin Unbuffered DIMM DDR3 SDRAM
http://www.supertalent.com/oem
Products and Specifications discussed herein are subject to change without notice
11.2 AC Timing Parameters & Specifications (con’t)
DDR3-1333
Parameter
Symbol
min
max
Units
Cumulative error across 11 cycles
tERR(11per)
- 210
210
ps
Cumulative error across 12 cycles
tERR(12per)
- 215
215
ps
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
tCK(avg)
Absolute clock Low pulse width
tCL(abs)
0.43
-
tCK(avg)
Data Timing
DQS, /DQS to DQ skew, per group, per access
tDQSQ
-
125
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK(avg)
DQ low-impedance time from CK, /CK
tLZ(DQ)
-500
250
ps
DQ high-impedance time from CK, /CK
tHZ(DQ)
-
250
ps
Data setup time to DQS, /DQS referenced to Vih(ac)Vil(ac) levels
tDS(base)
TBD
-
ps
Data hold time to DQS, /DQS referenced to Vih(ac)Vil(ac) levels
tDH(base)
TBD
-
ps
DQ and DM Input pulse width for each input
tDIPW
400
-
ps
Data Strobe Timing
DQS, /DQS READ Preamble tRPRE
0.9
-
tCK
DQS, /DQS differential READ Postamble
tRPST
0.3
-
tCK
DQS, /DQS output high time
tQSH
0.4
-
tCK(avg)
DQS, /DQS output low time
tQSL
0.4
-
tCK(avg)
DQS, /DQS WRITE Preamble
tWPRE
0.9
-
tCK
DQS, /DQS WRITE Postamble
tWPST
0.3
-
tCK
DQS, /DQS rising edge output access time from rising CK, /CK
tDQSCK
-255
255
ps
DQS, /DQS low-impedance time (Referenced from RL-1)
tLZ(DQS)
-500
250
ps
DQS, /DQS high-impedance time (Referenced from RL+BL/2)
tHZ(DQS)
250
-
ps
DQS, DQS differential input low pulse width
tDQSL
0.45
0.55
tCK
DQS, DQS differential input high pulse width
tDQSH
0.45
0.55
tCK
DQS, DQS rising edge to CK, CK rising edge
tDQSS
-0.25
0.25
tCK(avg)
DQS,DQS faling edge setup time to CK, CK rising edge
tDSS
0.2
-
tCK(avg)
DQS,DQS faling edge hold time to CK, CK rising edge
tDSH
0.2
-
tCK(avg)
DLL locking time
tDLLK
512
- nCK
internal READ Command to PRECHARGE Command delay
tRTP
max
(4tCK,7.5ns)
-
Delay from start of internal write transaction to internal read command
tWTR
max
(4tCK,7.5ns)
-
WRITE recovery time
tWR
15
- ns
Mode Register Set command cycle time
tMRD
4 -
nCK
Mode Register Set command update delay
tMOD
max
7
© 2006 Super Talent Tech., Corporation.
(12tCK,15ns)
-
CAS# to CAS# command delay
tCCD
4 -
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
nCK