Microchip Technology 24LC512-I/SN Memory IC 512 K 64 K x 8 24LC512-I/SN データシート

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24LC512-I/SN
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24AA512/24LC512/24FC512
DS21754M-page 6
 2010 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1 and A2 Chip Address 
Inputs
The A0, A1 and A2 inputs are used by the 24XX512 for
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
CC
 or V
SS
.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the chip address pins must be driven to logic ‘0’ or logic
‘1’ before normal device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
 (typical 10 k
 for 100 kHz, 2 kfor
400 kHz  and  1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
 or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24XX512 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX512 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the
master device determines which mode is activated.
Name
PDIP
SOIC
SOIJ
TSSOP
14-lead 
TSSOP
DFN
CS
Function
A0
1
1
1
1
1
1
3
User Configured Chip Select
A1
2
2
2
2
2
2
2
User Configured Chip Select
(NC)
3, 4, 5
Not Connected
A2
3
3
3
3
6
3
5
User Configured Chip Select
V
SS
4
4
4
4
7
4
8
Ground
SDA
5
5
5
5
8
5
6
Serial Data
SCL
6
6
6
6
9
6
7
Serial Clock
(NC)
10, 11, 12
Not Connected
WP
7
7
7
7
13
7
4
Write-Protect Input
V
CC
8
8
8
8
14
8
1
+1.7V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+1.7V to 5.5V (24FC512)