Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート

ARM DDI0198D

9-5

The following sequence corresponds to steps 1-4 in IMB operation on page 9-3:

clean_loop

MRC p15, 0, r15, c7, c10, 3 ; clean entire dcache using test and clean
BNE clean_loop

MCR p15, 0, r0, c7, c10, 4

; drain write buffer

STR rx,[ry]

; nonbuffered store to signal L2 world to

 

; synchronize

MCR p15, 0, r0, c7, c5, 0

; invalidate icache

The following sequence illustrates an IMB sequence used after modifying a single 
instruction (for example, setting a software breakpoint), with no external 
synchronization required:

STR rx,[ry]                   ; store that modifies instruction at address ry
MCR p15, 0, ry, c7, c10, 1    ; clean dcache single entry (MVA)
MCR p15, 0, r0, c7, c10, 4    ; drain write buffer
MCR p15, 0, ry, c7, c5,  1    ; invalidate icache single entry (MVA)