Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート

ARM DDI0198D

A-5

Table A-2 describes the ARM926EJ-S processor coprocessor interface signals.

Output

Indicates 

STC

/

LDC

 operation aborted. Asserted in WB 

stage of coprocessor pipeline.

Output

Indicates number of words to be transferred for 

LDC

/

STC

 operation. If no external coprocessors are 

attached, this must be tied to b0000.

Coprocessor clock 
enable

Output

Coprocessor clock enable. When HIGH on the rising 
edge of CLK the pipeline follower logic can 
advance.

Coprocessor write data

Input

The coprocessor data bus for transferring data from 
the coprocessor.

Coprocessor read data

Output

The coprocessor data bus for transferring data to the 
coprocessor.

CPEN Coprocessor 
enable

Input

When LOW disables the external coprocessor 
interface. If CPEN is LOW then CHSDE and 
CHSEX must both be driven to b10 (ABSENT 
response).

Coprocessor 
instruction data

Output

The coprocessor instruction bus that instructions are 
transferred over to the pipeline follower in the 
coprocessor.

Output

Indicates that there is a coprocessor instruction in the 
Execute stage of the pipeline, that must be executed.

Output

If HIGH during the first Memory cycle of a 
coprocessor instruction, then the coprocessor must 
cancel the instruction without changing any internal 
state.

Coprocessor 
handshake decode

Output

The handshake signals from the Decode stage of the 
coprocessor pipeline follower. Indicates ABSENT 
(b10), WAIT (b00), GO (b01), or LAST (b11). If no 
external coprocessors are attached this must be tied to 
b10 (ABSENT response).