Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート

2

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

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Core

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ARM926EJ-S™ ARM

®

 Thumb

®

 Processor running up to 400 MHz

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16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit

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Memories

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One 128-Kbyte internal ROM embedding standard or secure bootstrap routine

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One 32-Kbyte internal SRAM, single-cycle access at system speed

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32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories

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MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC)

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System running up to 133 MHz

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Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real 
Time Clock

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Boot Mode Select Option, Remap Command

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Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators

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Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL 
optimized for USB

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Six 32-bit-layer AHB Bus Matrix

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Dual Peripheral Bridge with dedicated programmable clock

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One dual port 8-channel DMA Controller

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Advanced Interrupt Controller and Debug Unit

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Two Programmable External Clock Signals

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Low-power Mode

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Shut Down Controller with four 32-bit battery backup registers

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Clock Generator and Power Management Controller

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Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities

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Peripherals

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LCD Controller

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USB Device Full Speed with dedicated On-Chip Transceiver

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USB Host Full Speed with dedicated On-Chip Transceiver

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One High speed SD card and SDIO Host Controller

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Two Master/Slave Serial Peripheral Interfaces

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Two Three-channel 32-bit Timer/Counters

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One Synchronous Serial Controller

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One Four-channel 16-bit PWM Controller

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Two Two-wire Interfaces

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Four USARTs, two UARTs, one DBGU

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One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touch screen support

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Safety

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Crystal Failure Detection

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Independent Watchdog

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Power-on Reset Cells

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Write Protection Registers

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SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2, see the device configuration table in