Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート
製品コード
AT91SAM9N12-EK
52
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
10.4.2 Test
Environment
shows a test environment example. Test vectors are sent and interpreted by the tester. In this
example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to
form a single scan chain.
form a single scan chain.
Figure 10-3. Application Test Environment Example
10.5
Debug and Test Pin Description
JTAG
Interface
ICE/JTAG
Connector
AT91SAM9-based Application Board In Test
AT91SAM9
Test Adaptor
Chip 2
Chip n
Chip 1
Tester
Table 10-1. Debug and Test Pin List
Pin Name
Function
Type
Active Level
Reset/Test
NRST
Microcontroller Reset
Input/Output
Low
ICE and JTAG
NTRST
Test Reset Signal
Input
Low
TCK
Test Clock
Input
TDI
Test Data In
Input
TDO
Test Data Out
Output
TMS
Test Mode Select
Input
RTCK
Returned Test Clock
Output
JTAGSEL
JTAG Selection
Input
Debug Unit
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output