Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート

579

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

–Both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled)

–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is 

able to prefetch data and write HSMCI simultaneously.

8.

Configure the fields of DMAC_CFGx for Channel x as follows:

–FIFOCFG defines the watermark of the DMA channel FIFO.

–SRC_H2SEL is set to true to enable hardware handshaking on the destination.

–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host 

Controller.

–Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.

3.

Wait for XFRDONE in the HSMCI_SR. 

1.

Wait until the current command execution has successfully terminated.

1.

Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.

2.

Program the block length in the card. This value defines the value block_length.

3.

Program the block length in the HSMCI Configuration Register with block_length value.

4.

Configure the fields of the HSMCI_DMA register as follows:



OFFSET field with dma_offset.



CHKSIZE is user defined.



DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit was previously set to 
false.

5.

Issue a WRITE_MULTIPLE_BLOCK command.

6.

Program the DMA Controller to use a list of descriptors. Each descriptor transfers one block of data. Block n of 
data is transferred with descriptor LLI(n).

1.

Read the channel register to choose an available (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the 
DMAC_EBCISR.

3.

Program a List of descriptors.

4.

The LLI(n).DMAC_SADDRx memory location for Channel x must be set to the location of the source data. 
When the first data location is not word aligned, the two LSB bits define the temporary value called 
dma_offset. The two LSB bits of LLI(n).DMAC_SADDRx must be set to 0.

5.

The LLI(n).DMAC_DADDRx register for Channel x must be set with the starting address of the 
HSMCI_FIFO address.

6.

Configure the fields of LLI(n).DMAC_CTRLAx for Channel x as follows:

–DST_WIDTH is set to WORD.

–SRC_WIDTH is set to WORD.

–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.

–BTSIZE is programmed with CEILING((block_length + dma_offset)/4).

7.

Configure the fields of LLI(n).DMAC_CTRLBx for Channel x as follows:

–DST_INCR is set to INCR.

–SRC_INCR is set to INCR.

–DST_DSCR is set to 0 (fetch operation is enabled for the destination).

–SRC_DSCR is set to 1 (source address is contiguous).

–FC field is programmed with memory to peripheral flow control mode.