Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD データシート
製品コード
ATSAM4S-WPIR-RD
509
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
Figure 29-2.
Master Clock Controller
29.5
Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the processor sleep mode. The
processor clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE (WaitForEvent) processor
instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode Register (PMC_FSMR).
The processor clock HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
The processor clock HCLK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The
processor sleep mode is achieved by disabling the processor clock, which is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
When processor sleep mode is entered, the current instruction is finished before the clock is stopped, but this does
When processor sleep mode is entered, the current instruction is finished before the clock is stopped, but this does
not prevent data transfers from other masters of the system bus.
29.6
SysTick Clock
The SysTick calibration value is fixed to 12500 which allows the generation of a time base of 1 ms with SysTick
clock to the maximum frequency on MCK divided by 8.
29.7
USB Clock Controller
The user can select the PLLA or the PLLB output as the USB source clock by writing the USBS bit in PMC_USB.
If using the USB, the user must program the PLL to generate an appropriate frequency depending on the USBDIV
bit in PMC_USB.
When the PLL output is stable, i.e., the LOCK bit is set:
When the PLL output is stable, i.e., the LOCK bit is set:
the USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this
peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR
gives the activity of this clock. The USB device port requires both the 48 MHz signal and the master clock.
The master clock may be controlled by means of the Master Clock Controller.
Figure 29-3.
USB Clock Controller
29.8
Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by means of the Peripheral
Clock Controller. The user can individually enable and disable the clock on the peripherals.
SLCK
Master Clock
Prescaler
To the MCK Divider
PRES
CSS
MAINCK
PLLACK
PLLBCK
To the Processor
Clock Controller (PCK)
Clock Controller (PCK)
PMC_MCKR
PMC_MCKR
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/3,.../16