Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD データシート

製品コード
ATSAM4S-WPIR-RD
ページ / 1231
761
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
36.7
Functional Description
36.7.1 Baud Rate Generator
The baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the 
transmitter.
The baud rate generator clock source can be selected by setting the USCLKS field in US_MR between:
The master clock MCK
A division of the master clock, the divider being product dependent, but generally set to 8
The external clock, available on the SCK pin
The baud rate generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate 
Generator register (US_BRGR). If a zero is written to CD, the baud rate generator does not generate any clock. If 
a one is written to CD, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin 
must be longer than a master clock (MCK) period. The frequency of the signal provided on SCK must be at least 3 
times lower than MCK in USART mode, or 6 times lower in SPI mode.
Figure 36-3.
Baud Rate Generator
36.7.1.1 Baud Rate in Asynchronous Mode 
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is 
field programmed in the US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then 
divided by 16 or 8, depending on the programming of the OVER bit in the US_MR. 
If OVER is set, the receiver sampling is eight times higher than the baud rate clock. If OVER is cleared, the 
sampling is performed at 16 times the baud rate clock.
The baud rate is calculated as per the following formula:
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that 
the OVER bit is set.
MCK/DIV
16-bit Counter
0
Baud Rate 
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling 
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
Baudrate
SelectedClock
8 2
Over
(
)CD
(
)
--------------------------------------------
=