Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1136
Datasheet
27
0h
RW
SRST_HOST12BUS:
soft reset bit for the bus from host to fifo adapters
26
0h
RW
SRST_NBUS:
soft reset bit for the narrow bus
25
0h
RW
SRST_OCP2CIO:
soft reset bit for the OCP2CIO converter
24
0h
RW
SRST_SP:
soft reset bit for the SP
23
0h
RW
SRST_SF_GDC2_CELLS:
soft reset bit for the FIFOs between the GDC2 and the cells
22
0h
RW
SRST_SF_GDC1_CELLS:
soft reset bit for the FIFOs between the GDC1 and the cells
21
0h
RW
SRST_SF_DMA_CELLS:
soft reset bit for the FIFOs between the DMA and the cells
20
0h
RW
SRST_SF_ISYS_SP:
soft reset bit for the FIFOs between the input system and the SP
19
0h
RW
SRST_SF_MC_SP:
soft reset bit for the FIFOs between the stream2memory and the SP
18
0h
RW
SRST_SF_SIF_SP:
soft reset bit for the FIFOs between the secondary input formatter
and the SP
17
0h
RW
SRST_SF_PIF_CELLS:
soft reset bit for the FIFOs between the primary input
formatters and the cells
16
0h
RW
SRST_SF_ISP_SP:
soft reset bit for the FIFOs between SP and ISP
15
0h
RW
SRST_DMA:
soft reset bit for the DMA
14
0h
RW
SRST_SLV_GRP_BUS:
soft reset bit for the slave group bus
13
0h
RW
SRST_ISP:
soft reset bit for the isp (vector processor)
12
0h
RW
SRST_VEC_BUS:
soft reset bit for the vector bus
11
0h
RW
SRST_GDC2:
soft reset bit for the GDC2 block
10
0h
RW
SRST_GDC1:
soft reset bit for the GDC1 block
9
0h
RW
SRST_IFT_SEC_PIPE:
soft reset bit for the CIO pipeline after the secondary input
formatter
8
0h
RW
SRST_OSYS:
soft reset bit for the blocks in the output system cluster
7
0h
RW
SRST_FACELLFIFOS:
soft reset bit for the fifo's connected to the fifo adapter between
host and cells
6
0h
RW
SRST_GPTIMER:
soft reset bit for the GP timer block
5
0h
RW
SRST_TC:
soft reset bit for the timed controller block
Bit
Range
Default &
Access
Description