Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2110
Datasheet
17.20.16 TX_DWORD15 (tx_dword15)—Offset 3Ch
Access Method
Default: 00000000h
11:8
0h
RW
ovisa1_lanesel_3_0:
VISA Lane Select for Lane1. Selects the byte of data to be sent
out on lane1.
7
0h
RW
ovisa_bypass:
VISA Bypass. Allows for signals to be passed asynchronously through
VISA block. Applies to both lane0 and lane1. 0 : Flop signals in local VISA block
(default) 1 : Bypass flops in local VISA block
6:4
0h
RW
ovisa0_clksel_2_0:
VISA Clock Select for Lane0. Selects the source synchronous
clock to be used for data being sent on lane0.
3:0
0h
RW
ovisa0_lanesel_3_0:
VISA Lane Select for Lane0. Selects data byte to be driven out
of VISA-0 byte. Can be either clocked or unclocked data
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
tx_dword15:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
se
rv
ed
551
re
se
rv
ed
550
re
se
rv
ed
549
re
se
rv
ed
548
re
se
rv
ed
547
re
se
rv
ed
546
re
se
rv
ed
545
re
se
rv
ed
544
Bit
Range
Default &
Access
Description
31:30
0h
RO
reserved551:
reserved
29:24
0h
RO
reserved550:
The slices used in R2 for DE (PstC=X,C=Y,PreC=Y)
23:22
0h
RO
reserved549:
reserved
21:16
0h
RO
reserved548:
The slices used in R2 for FS (PstC=X,C=Y,PreC=X)
15
0h
RO
reserved547:
reserved
14:8
0h
RO
reserved546:
The slices used in R1 for DE (PstC=X,C=Y,PreC=Y)
7
0h
RO
reserved545:
reserved
6:0
0h
RO
reserved544:
The slices used in R1 for FS (PstC=X,C=Y,PreC=X)