Intel E3815 FH8065301567411 データシート

Intel

®

 Atom™ Processor E3800 Product Family

2154

Datasheet

The RW/L property of this register is controlled by the ACCTRL bit.

Default: 00000000h

Default: 00000000h

3:0

0h

RW

This field controls whether SuperSpeed capability is 

enabled for a given USB3 port. When set to 1, Enables SS termination Enables PORTSC 

to to see the connects on the ports. When set to 0, Disables SS termination Blocks 

PORTSC from reporting attach/connect. Places port in the lowest power state.

SUS

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Rsvd1

US

B3S

S

EN

M

31:4

0000000h

RO

Reserved.

Core

3:0

0h

RW/L

This field allows the BIOS to communicate to 

the OS which USB 3.0 ports can have the SuperSpeed capabilities enabled. When set to 

1, The OS may enable or disable the SuperSpeed capabilities by modifying the 

corresponding USB3SSEN bit. When set to 0, The OS shall not modify the corresponding 

USB3SSEN bit. BIOS shall set this bit to a '1' if the corresponding USB3SSEN bit is RW, 

unless the BIOS has cleared the USB2HCSELM bit for a USB 2.0 port and the BIOS 

wishes the OS to disable the corresponding SuperSpeed terminations for that physical 

connector. Port to bit mapping is in one-hot encoding, i.e. bit 0 controls port 1 and so 

on.

Core

PCI Configuration Register

(Size: 32 bits)