Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2711
20.6.13
INTSTS—Offset 24h
Interrupt Status
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
G
LOBAL_INTE
RRUP
T
_ST
A
T
U
S
RESE
RVED
0
RESE
RVED
1
S
T
REA
M
_INTE
RRUP
T
_ST
A
T
U
S
Bit
Range
Default &
Access
Description
31
0h
RO
GLOBAL_INTERRUPT_STATUS:
This bit is an OR of all of the interrupt status bits in
this register.
30
0h
RO
RESERVED0:
Status of general controller interrupt. A 1 indicates that an interrupt
condition occurred due to a Response Interrupt a Response Buffer Overrun Interrupt
CORB Memory Error Interrupt Error Present Interrupt Intel Reserved or a SDIN State
Change event. The exact cause can be determined by interrogating other registers. Note
that a HW interrupt will not be generated unless the corresponding enable bit is set. This
bit is an OR of all of the stated interrupt status bits for this register.
29:8
0h
RO
RESERVED1:
reserved
7:0
00h
RW
STREAM_INTERRUPT_STATUS:
A 1 indicates that an interrupt condition occurred on
the corresponding Stream. Note that a HW interrupt will not be generated unless the
corresponding enable bit is set. This bit is an OR of all of an individual stream s interrupt
status bits. The streams are numbered and the SIS bits assigned sequentially based on
their order in the register set. Bit 0 Input Stream 1 Bit 1 Input Stream 2 Bit 2 Input
Stream 3 Bit 3 Input Stream 4 Bit 4 Output Stream 1 Bit 5 Output Stream 2 Bit 6 Output
Stream 3 Bit 7 Output Stream 4