Intel E3815 FH8065301567411 データシート
製品コード
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
428
Datasheet
14.9.13
GGC—Offset 50h
GMCH Graphics Control Register. SOXi Context Save/Restore : Yes Note : CDV
supported 64MB maximum. CDV had no GGMS field. Note : CDV had more granularity
on the encodings for graphics mode select and only 3 bits.
Access Method
Default: 00000028h
15:8
01h
RO
INTERRUPT_PIN (INTERRUPT_PIN_1):
IPIN: Value indicates which interrupt pin
this device uses. This field is hard coded to 1h since Valleyview Device 2 is a single
function device. The PCI spec requires that it use INTA#.01h: INTA
7:0
00h
RW
INTRLINE (INTRLINE_0):
ILIN: BIOS written value to communicate interrupt line
routing information to the device driverUsed to communicate interrupt line routing
information. POST software writes the routing information into this register as it
initializes and configures the system. The value in this register indicates to which input
of the system interrupt controller the device?s interrupt pin is connected.
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 32 bits)
GGC:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
RSV
D
0
RSV
D
_0
VA
M
E
N
_
1
RSV
D
_2
GGM
S_3
GM
S_4
RSV
D
_5
VG
A_DIS
A
BLE
_
6
GGCL
C
K_7
Bit
Range
Default &
Access
Description
31:16
0b
RO
RSVD0:
Reserved
15
0b
RO
RSVD (RSVD_0):
Reserved
14
0b
RW/L
VAMEN (VAMEN_1):
Enables the use of the iGFX engines for Versatile Acceleration. 1
- iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is 048000h. 0 -
iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h.
13:10
0h
RO
RSVD (RSVD_2):
Reserved
9:8
00b
RW/L
GGMS (GGMS_3):
GTT Graphics Memory Size (GGMS): This field is used to select the
amount of Main Memory that is pre-allocated to support the Internal Graphics
Translation Table. The BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled. GSM is assumed to be a contiguous physical DRAM space with DSM,
and BIOS needs to allocate a contiguous memory chunk. Hardware will drive the base of
GSM from DSM only using the GSM size programmed in the register. 0h: No memory
pre-allocated. GTT cycles (Mem and IO) are not claimed. 1h: 1 MB of memory pre-
allocated for GTT. 2h: 2 MB of memory pre-allocated for GTT. 3h: Reserved. All
unspecified encodings of this register field are reserved, hardware functionality is not
guaranteed if used.