Bosch TTCAN ユーザーズマニュアル
User’s Manual
BOSCH
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Revision 1.6
TTCAN
11.11.02
manual_about.fm
In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The
edge is “
edge is “
late
” since it occurs after the Sync_Seg. Reacting to the “
late
” edge, Phase_Seg1 is
lengthened so that the distance from the edge to the Sample Point is the same as it would
have been from the Sync_Seg to the Sample Point if no edge had occurred. The phase error
of this “
have been from the Sync_Seg to the Sample Point if no edge had occurred. The phase error
of this “
late
” edge is less than SJW, so it is fully compensated and the edge from dominant to
recessive at the end of the bit, which is one nominal bit time long, occurs in the Sync_Seg.
In the second example an edge from recessive to dominant occurs during Phase_Seg2. The
edge is “
edge is “
early
” since it occurs before a Sync_Seg. Reacting to the “
early
” edge, Phase_Seg2
is shortened and Sync_Seg is omitted, so that the distance from the edge to the Sample Point
is the same as it would have been from an Sync_Seg to the Sample Point if no edge had
occurred. As in the previous example, the magnitude of this “
is the same as it would have been from an Sync_Seg to the Sample Point if no edge had
occurred. As in the previous example, the magnitude of this “
early
” edge’s phase error is less
than SJW, so it is fully compensated.
The Phase Buffer Segments are lengthened or shortened temporarily only; at the next bit time,
the segments return to their nominal programmed values.
the segments return to their nominal programmed values.
In these examples, the bit timing is seen from the point of view of the CAN implementation’s
state machine, where the bit time starts and ends at the Sample Points. The state machine
omits Sync_Seg when synchronising on an “
state machine, where the bit time starts and ends at the Sample Points. The state machine
omits Sync_Seg when synchronising on an “
early
” edge because it cannot subsequently
redefine that time quantum of Phase_Seg2 where the edge occurs to be the Sync_Seg.
The examples in figure 12 show how short dominant noise spikes are filtered by
synchronisations. In both examples the spike starts at the end of Prop_Seg and has the length
of (Prop_Seg + Phase_Seg1).
synchronisations. In both examples the spike starts at the end of Prop_Seg and has the length
of (Prop_Seg + Phase_Seg1).
In the first example, the Synchronisation Jump Width is greater than or equal to the phase
error of the spike’s edge from recessive to dominant. Therefore the Sample Point is shifted
after the end of the spike; a recessive bus level is sampled.
error of the spike’s edge from recessive to dominant. Therefore the Sample Point is shifted
after the end of the spike; a recessive bus level is sampled.
In the second example, SJW is shorter than the phase error, so the Sample Point cannot be
shifted far enough; the dominant spike is sampled as actual bus level.
shifted far enough; the dominant spike is sampled as actual bus level.
Figure 12: Filtering of Short Dominant Spikes
recessive
dominant
Sync_Seg
Prop_Seg
Phase_Seg1
Phase_Seg2
Spike
Rx-Input
Sample-Point
Sample-Point
Sample-Point
Sample-Point
recessive
dominant
Spike
Rx-Input
SJW
≥
Phase Error
SJW < Phase Error