Motorola DSP56012 ユーザーズマニュアル
4-66
DSP56012 User’s Manual
MOTOROLA
Parallel Host Interface
Host Interface (HI)
4.4.8.4.2
Overwriting Transmit Byte Registers
The host programmer should not write to the transmit byte registers, TXH, TXM, or
TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty.
This guarantees that the DSP will read stable data when it reads the HORX register.
TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty.
This guarantees that the DSP will read stable data when it reads the HORX register.
4.4.8.4.3
Synchronization of Status Bits from DSP to Host
HC, HOREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared
from inside the HI and read by the host processor. The host can read these status bits
very quickly without regard to the clock rate used by the DSP, but there is a chance
that the state of the bit could be changing during the read operation. This possible
change is generally not a system problem, since the bit will be read correctly in the
next pass of any host polling routine.
from inside the HI and read by the host processor. The host can read these status bits
very quickly without regard to the clock rate used by the DSP, but there is a chance
that the state of the bit could be changing during the read operation. This possible
change is generally not a system problem, since the bit will be read correctly in the
next pass of any host polling routine.
However, if the host holds HEN for the minimum assertion time plus x clock cycles
(see “Host Port Usage Considerations” in the
(see “Host Port Usage Considerations” in the
DSP56012 Technical Data
sheet
(DSP56012/D) for the minimum number of cycles), the status data is guaranteed to
be stable. The x clock cycles are used to synchronize the HEN signal and block
internal updates of the status bits. There is no other minimum HEN assertion time
relationship to DSP clocks. There is a minimum HEN deassertion time so that the
blocking latch can be updated if the host is in a tight polling loop. This minimum
time only applies to reading status bits.
be stable. The x clock cycles are used to synchronize the HEN signal and block
internal updates of the status bits. There is no other minimum HEN assertion time
relationship to DSP clocks. There is a minimum HEN deassertion time so that the
blocking latch can be updated if the host is in a tight polling loop. This minimum
time only applies to reading status bits.
The only potential problem with the host processor’s reading of status bits would be
its reading HF3 and HF2 as an encoded pair. For example, if the DSP changes HF3
and HF2 from “00” to “11”, there is a small possibility that the host could read the
bits during the transition and receive “01” or “10” instead of “11”. If the combination
of HF3 and HF2 has significance, the host processor could potentially read the wrong
combination. Two solutions would be to 1) read the bits twice and check for
consensus, or 2) hold HEN access for HEN + x clock cycles so that status bit
transitions are stabilized.
its reading HF3 and HF2 as an encoded pair. For example, if the DSP changes HF3
and HF2 from “00” to “11”, there is a small possibility that the host could read the
bits during the transition and receive “01” or “10” instead of “11”. If the combination
of HF3 and HF2 has significance, the host processor could potentially read the wrong
combination. Two solutions would be to 1) read the bits twice and check for
consensus, or 2) hold HEN access for HEN + x clock cycles so that status bit
transitions are stabilized.
4.4.8.4.4
Overwriting the Host Vector
The host programmer should change the host vector register only when the HC bit is
clear. This will guarantee that the DSP interrupt control logic will receive a stable
vector.
clear. This will guarantee that the DSP interrupt control logic will receive a stable
vector.
4.4.8.4.5
Cancelling a Pending Host Command interrupt
The host processor can elect to clear the HC bit to cancel the host command interrupt
request at any time before it is recognized by the DSP. The DSP CPU can execute the
host interrupt after the HC bit is cleared because the host processor does not know
exactly when the interrupt will be recognized. This uncertainty in timing is due to
differences in synchronization between the host processor and DSP CPU and the
request at any time before it is recognized by the DSP. The DSP CPU can execute the
host interrupt after the HC bit is cleared because the host processor does not know
exactly when the interrupt will be recognized. This uncertainty in timing is due to
differences in synchronization between the host processor and DSP CPU and the