Motorola DSP56012 ユーザーズマニュアル

Interrupt priorities are determined in the 24-bit Interrupt Priority Register (IPR). The 
Interrupt Priority Level (IPL) for each on-chip peripheral device and for two of the 
external interrupt sources can be programmed, under software control, to one of 
three maskable priority levels (IPL 0,1 or 2). IPLs are set by writing to the IPR. The 
IPR configuration is shown in 

• Bits 5–0 of the IPR are used by the DSP56000 core for two of the external 

interrupt request inputs, IRQA (IAL [2:0]) and IRQB (IBL[2:0]); assuming the 
same IPL, IRQA has higher a priority than IRQB.

• Bits 9–6 and 23–18 are reserved for future use.

• Bits 17–10 are available for determining IPLs for each peripheral (Host, SHI, 

DAX, SAI). Two IPL bits are required for each peripheral interrupt group.

The interrupt priorities are shown in 

vectors are shown in