Philips P89LPC902 ユーザーズマニュアル
Philips Semiconductors
User’s Manual - Preliminary -
P89LPC901/902/903
TIMERS 0 AND 1
45
5. TIMERS 0 AND 1
The P89LPC901/902/903 has two general-purpose counter/timers which are similar to the 80C51 Timer 0 and Timer 1. Timer 0
of the P89LPC901 can be configured to operate either as a timer or event counter (see Figure 5-1). An option to automatically
toggle the T0 pin upon timer overflow has been added. Timer 1 of the P89LPC901 and both Timer 0 and Timer 1 of the
P89LPC902 and P89LPC903 devices may only function as timers.
of the P89LPC901 can be configured to operate either as a timer or event counter (see Figure 5-1). An option to automatically
toggle the T0 pin upon timer overflow has been added. Timer 1 of the P89LPC901 and both Timer 0 and Timer 1 of the
P89LPC902 and P89LPC903 devices may only function as timers.
In the “Timer” function, the timer is incremented every PCLK.
In the “Counter” function, the Timer 0 register is incremented in response to a 1-to-0 transition on the external input pin, T0, which
is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is
incremented. The new count value appears in the register during the cycle following the one in which the transition was detected.
Since it takes 2 machine cycles (4 CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is 1/4 of the CPU clock
frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at
least once before it changes, it should be held for at least one full machine cycle.
is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is
incremented. The new count value appears in the register during the cycle following the one in which the transition was detected.
Since it takes 2 machine cycles (4 CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is 1/4 of the CPU clock
frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at
least once before it changes, it should be held for at least one full machine cycle.
The “Timer” or “Counter” function is selected by control bit T0C/T in the Special Function Register TMOD. Timer 0 and Timer 1
of the P89LPC902 and P89LPC903, and Timer 1 of the P89LPC901 have four operating modes (modes 0, 1, 2, and 3), which
are selected by bit-pairs (TnM1, TnM0) in TMOD. Modes 0, 1, 2 and 3 are the same for both Timers. Mode 3 is different. The
operating modes are described later in this section. In addition to these modes, Timer 0 of the P89LPC901 has mode 6.
Additionally the T0M2 mode bit in TAMOD is used to specify modes with Timer 0 of the P89LPC901.
of the P89LPC902 and P89LPC903, and Timer 1 of the P89LPC901 have four operating modes (modes 0, 1, 2, and 3), which
are selected by bit-pairs (TnM1, TnM0) in TMOD. Modes 0, 1, 2 and 3 are the same for both Timers. Mode 3 is different. The
operating modes are described later in this section. In addition to these modes, Timer 0 of the P89LPC901 has mode 6.
Additionally the T0M2 mode bit in TAMOD is used to specify modes with Timer 0 of the P89LPC901.
Figure 5-1: Timer/Counter Mode Control register (TMOD)
TMOD
Address: 89h
Address: 89h
Not bit addressable
Reset Source(s): Any source
Reset Value:
Reset Source(s): Any source
Reset Value:
00000000B
BIT
SYMBOL
FUNCTION
TMOD.7
-
Reserved.
TMOD.6
-
Reserved.
TMOD.5, 4
T1M1,T1M0
Mode Select for Timer 1. These bits are used to determine the Timer 1 mode (see Figure
5-2).
5-2).
TMOD.3
-
Reserved.
TMOD.2
T0C/T
Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from CCLK). Set
for Counter operation (input from T0 input pin).P89LPC901. When writing to this register
on the P89LPC902 or P89LPC903 devices, this bit position should be written with a zero.
for Counter operation (input from T0 input pin).P89LPC901. When writing to this register
on the P89LPC902 or P89LPC903 devices, this bit position should be written with a zero.
TMOD.1, 0
T0M1,T0M0
Mode Select for Timer 0. These bits are used to determine the Timer 0 mode (see Figure
5-2). On the P89LPC901 these bits are used with the T0M2 bit in the TAMOD register to
determine the Timer 0 mode (see Figure 5-2).
5-2). On the P89LPC901 these bits are used with the T0M2 bit in the TAMOD register to
determine the Timer 0 mode (see Figure 5-2).
7
6
5
4
3
2
1
0
-
-
T1M1
T1M0
-
T0C/T
T0M1
T0M0