Fujitsu MB91191 ユーザーズマニュアル
155
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Reel Mask Timer Control Register (RLxMTC)
Figure 6.4-5 Reel mask timer control register (RLxMTC)
[bit7 to 0]:D7 to 0
The masking period control of the reel input is performed by the set value. When
ΦMT is specified as
the clock cycle time selected by the mask timer clock select (CS) bit of the reel control register, and N
is specified as the set value, the drum input masking period TM is as follow.
TM =
ΦMT × N ± ΦMT/2. However, N is set to 0, the mask processing does not perform.
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Operation of Reel Input
Refer to "6.2 Capstan Input" for the 8-bit programmable divider and mask timer operations.
7 6 5 4 3 2 1 0
XXXX XXXX
B
Initial value
bit
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access