Fujitsu MB91191 ユーザーズマニュアル
243
[bit5]:HCIE
It is hard conversion interrupt enable bit.
The interrupt request is generated when HCEF=1 is HCIE=1.
[bit2]:HFCR
It is hard conversion FIFO clear bit.
The read value of this bit is always "0".
[bit1]:HFUL
It is hard conversion FIFO full bit.
[bit0]:HEMP
It is hard conversion FIFO empty bit.
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Hard Conversion FIFO Data Register (HCFD)
Figure 16.2-7 Hard conversion FIFO data register (HCFD)
It is conversion result register for hard start. Reading this register enables data to be fetched sequentially.
[bit15]:RS
It is hard conversion request status.
0 Interruption
interdiction
1 Interruption
permission
0 None
1 Clear
FIFO.
0
Status that data can input to FIFO
1
Status of FIFO full
0
Status that data is retained in FIFO
1
Status of FIFO empty
XXXX --XX
H
XXXX XXXX
H
Initial value
bit
R
RS
C2
C1
C0
D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address: 0000AA
H
Access
0 ADST0
(PPG0)
1 ADST1
(PPG1,
RTG)