Fujitsu MB91191 ユーザーズマニュアル
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CHAPTER 3 CPU
- After saving the register, fetches in the interrupt vector and executes from the processing routine.
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When the level of the interrupt is disabled by the I flag of CPU ILM
- Executes the instruction the following instruction that changed to the stop status.
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Return by RST pin
Returning from stop status to normal operating status is as per the following procedure.
L level application to the RST pin -> Generates an internal reset -> Restarts oscillation circuit operation ->
Waits for oscillation stabilization -> After stabilization, restarts supply of internal peripheral clock ->
Restarts supply of internal bus clock -> Restarts supply of internal CPU clock -> Fetches in the reset vector
-> Restarts the command execution from the reset entry address
Notes:
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If an interrupt request has already been generated from a peripheral, status is not changed to stop, and
writing is ignored.
writing is ignored.
•
No internal clocks are supplied while waiting for oscillation stabilization except for power-on reset. For
power-on reset, the internal status needs to be initialized, so all internal clocks are supplied.
power-on reset, the internal status needs to be initialized, so all internal clocks are supplied.