データシート (AT91SAM9G25-EK)目次Section 15Introduction51.1 Scope51.2 Applicable Documents6Section 27Kit Contents72.1 Deliverables72.2 Evaluation Board Specifications82.3 Electrostatic Warning9Section 310Power Up103.1 Power Up the Board103.2 DevStart103.3 Recovery Procedure113.4 Sample Code and Technical Support11Section 412Evaluation Kit Hardware124.1 Introduction124.2 Computer Module (CM)144.2.1 CM Board Overview144.2.2 Equipment List144.2.3 Function Blocks164.2.4 Configuration254.2.5 Connectors264.2.6 Schematics274.3 EK Board Description324.3.1 EK Board Overview324.3.2 Equipment List334.3.3 Function Blocks344.3.4 Configuration504.3.5 Connectors564.3.6 Schematics744.4 Optional Display Module (DM) Board Hardware894.4.1 DM Board Overview894.4.2 Equipment List894.4.3 Function Blocks894.4.4 Schematics93Section 594Revision History945.1 Revision History94サイズ： 6.38MBページ数： 95Language: Englishマニュアルを開く
データシート (AT91SAM9G25-EK)目次Description11. Features22. Block Diagram43. Signal Description54. Package and Pinout94.1 Overview of the 217-ball BGA Package94.2 Overview of the 247-ball BGA Packages104.2.1 247-ball TFBGA Package104.2.2 247-ball VFBGA Package104.3 I/O Description114.3.1 Reset State124.4 217-ball BGA Package Pinout134.5 247-ball BGA Package Pinout195. Power Considerations265.1 Power Supplies266. Memories276.1 Memory Mapping286.2 Embedded Memories286.2.1 Internal SRAM286.2.2 Internal ROM286.3 External Memories286.3.1 External Bus Interface286.3.2 Static Memory Controller286.3.3 DDR2SDR Controller297. System Controller307.1 Chip Identification327.2 Backup Section328. Peripherals338.1 Peripheral Mapping338.2 Peripheral Identifiers338.3 Peripheral Signal Multiplexing on I/O Lines349. ARM926EJ-S™359.1 Description359.2 Embedded Characteristics359.3 Block Diagram379.4 ARM9EJ-S Processor389.4.1 ARM9EJ-S Operating States389.4.2 Switching State389.4.3 Instruction Pipelines389.4.4 Memory Access389.4.5 Jazelle Technology389.4.6 ARM9EJ-S Operating Modes399.4.7 ARM9EJ-S Registers399.4.7.1 Status Registers409.4.7.2 Exceptions419.4.8 ARM Instruction Set Overview429.4.9 New ARM Instruction Set439.4.10 Thumb Instruction Set Overview449.5 CP15 Coprocessor459.5.1 CP15 Registers Access469.6 Memory Management Unit (MMU)479.6.1 Access Control Logic479.6.2 Translation Look-aside Buffer (TLB)479.6.3 Translation Table Walk Hardware489.6.4 MMU Faults489.7 Caches and Write Buffer489.7.1 Instruction Cache (ICache)489.7.2 Data Cache (DCache) and Write Buffer499.7.2.1 DCache499.7.2.2 Write Buffer499.8 Bus Interface Unit509.8.1 Supported Transfers509.8.2 Thumb Instruction Fetches509.8.3 Address Alignment5010. Debug and Test5110.1 Description5110.2 Embedded Characteristics5110.3 Block Diagram5210.4 Application Examples5310.4.1 Debug Environment5310.4.2 Test Environment5410.5 Debug and Test Pin Description5510.6 Functional Description5610.6.1 Test Pin5610.6.2 EmbeddedICE™5610.6.3 JTAG Signal Description5610.6.4 Debug Unit5610.6.5 IEEE 1149.1 JTAG Boundary Scan5710.6.6 JTAG ID Code Register5811. Boot Strategies5911.1 ROM Code5911.2 Flow Diagram5911.3 Chip Setup6011.4 NVM Boot6011.4.1 NVM Boot Sequence6011.4.2 NVM Bootloader Program Description6211.4.3 Valid Code Detection6311.4.3.1 ARM Exception Vectors Check6311.4.3.2 boot.bin File Check6411.4.4 Detailed Memory Boot Procedures6411.4.4.1 NAND Flash Boot: NAND Flash Detection6411.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction6711.4.4.3 SD Card Boot6911.4.4.4 SPI Flash Boot6911.4.4.5 TWI EEPROM Boot6911.4.5 Hardware and Software Constraints6911.5 SAM-BA Monitor7111.5.1 Command List7111.5.2 DBGU Serial Port7211.5.2.1 Supported External Crystal/External Clocks7211.5.2.2 Xmodem Protocol7211.5.3 USB Device Port7311.5.3.1 Supported External Crystal / External Clocks7311.5.3.2 USB Class7311.5.3.3 Enumeration Process7311.5.3.4 Communication Endpoints7412. Boot Sequence Controller (BSC)7512.1 Description7512.2 Embedded Characteristics7512.3 Product Dependencies7512.4 Boot Sequence Controller (BSC) User Interface7612.4.1 Boot Sequence Configuration Register7613. Advanced Interrupt Controller (AIC)7713.1 Description7713.2 Embedded Characteristics7713.3 Block Diagram7813.4 Application Block Diagram7813.5 AIC Detailed Block Diagram7813.6 I/O Line Description7913.7 Product Dependencies7913.7.1 I/O Lines7913.7.2 Power Management7913.7.3 Interrupt Sources7913.8 Functional Description8013.8.1 Interrupt Source Control8013.8.1.1 Interrupt Source Mode8013.8.1.2 Interrupt Source Enabling8013.8.1.3 Interrupt Clearing and Setting8013.8.1.4 Interrupt Status8013.8.2 Interrupt Latencies8213.8.3 Normal Interrupt8313.8.3.1 Priority Controller8313.8.3.2 Interrupt Nesting8313.8.3.3 Interrupt Vectoring8413.8.3.4 Interrupt Handlers8413.8.4 Fast Interrupt8513.8.4.1 Fast Interrupt Source8513.8.4.2 Fast Interrupt Control8513.8.4.3 Fast Interrupt Vectoring8513.8.4.4 Fast Interrupt Handlers8613.8.4.5 Fast Forcing8613.8.5 Protect Mode8713.8.6 Spurious Interrupt8813.8.7 General Interrupt Mask8813.9 Write Protection Registers8913.10 Advanced Interrupt Controller (AIC) User Interface9013.10.1 Base Address9013.10.2 AIC Source Mode Register9113.10.3 AIC Source Vector Register9213.10.4 AIC Interrupt Vector Register9313.10.5 AIC FIQ Vector Register9413.10.6 AIC Interrupt Status Register9513.10.7 AIC Interrupt Pending Register9613.10.8 AIC Interrupt Mask Register9713.10.9 AIC Core Interrupt Status Register9813.10.10 AIC Interrupt Enable Command Register9913.10.11 AIC Interrupt Disable Command Register10013.10.12 AIC Interrupt Clear Command Register10113.10.13 AIC Interrupt Set Command Register10213.10.14 AIC End of Interrupt Command Register10313.10.15 AIC Spurious Interrupt Vector Register10413.10.16 AIC Debug Control Register10513.10.17 AIC Fast Forcing Enable Register10613.10.18 AIC Fast Forcing Disable Register10713.10.19 AIC Fast Forcing Status Register10813.10.20 AIC Write Protect Mode Register10913.10.21 AIC Write Protect Status Register11014. Reset Controller (RSTC)11114.1 Description11114.2 Embedded Characteristics11114.3 Block Diagram11214.4 Functional Description11314.4.1 Reset Controller Overview11314.4.2 NRST Manager11314.4.2.1 NRST Signal11314.4.2.2 NRST External Reset Control11314.4.3 BMS Sampling11414.4.4 Reset States11414.4.4.1 General Reset11414.4.4.2 Wake-up Reset11514.4.4.3 User Reset11614.4.4.4 Software Reset11714.4.4.5 Watchdog Reset11814.4.5 Reset State Priorities11914.4.6 Reset Controller Status Register12014.5 Reset Controller (RSTC) User Interface12114.5.1 Reset Controller Control Register12214.5.2 Reset Controller Status Register12314.5.3 Reset Controller Mode Register12415. Real-time Clock (RTC)12515.1 Description12515.2 Embedded Characteristics12515.3 Block Diagram12615.4 Product Dependencies12715.4.1 Power Management12715.4.2 Interrupt12715.5 Functional Description12715.5.1 Reference Clock12715.5.2 Timing12715.5.3 Alarm12715.5.4 Error Checking when Programming12815.5.5 Updating Time/Calendar12815.6 Real-time Clock (RTC) User Interface13015.6.1 RTC Control Register13115.6.2 RTC Mode Register13215.6.3 RTC Time Register13315.6.4 RTC Calendar Register13415.6.5 RTC Time Alarm Register13515.6.6 RTC Calendar Alarm Register13615.6.7 RTC Status Register13715.6.8 RTC Status Clear Command Register13815.6.9 RTC Interrupt Enable Register13915.6.10 RTC Interrupt Disable Register14015.6.11 RTC Interrupt Mask Register14115.6.12 RTC Valid Entry Register14216. Periodic Interval Timer (PIT)14316.1 Description14316.2 Embedded Characteristics14316.3 Block Diagram14416.4 Functional Description14516.5 Periodic Interval Timer (PIT) User Interface14616.5.1 Periodic Interval Timer Mode Register14716.5.2 Periodic Interval Timer Status Register14816.5.3 Periodic Interval Timer Value Register14916.5.4 Periodic Interval Timer Image Register15017. Watchdog Timer (WDT)15117.1 Description15117.2 Embedded Characteristics15117.3 Block Diagram15217.4 Functional Description15317.5 Watchdog Timer (WDT) User Interface15517.5.1 Watchdog Timer Control Register15617.5.2 Watchdog Timer Mode Register15717.5.3 Watchdog Timer Status Register15818. Shutdown Controller (SHDWC)15918.1 Description15918.2 Embedded Characteristics15918.3 Block Diagram15918.4 I/O Lines Description16018.5 Product Dependencies16018.5.1 Power Management16018.6 Functional Description16018.7 Shutdown Controller (SHDWC) User Interface16118.7.1 Shutdown Control Register16218.7.2 Shutdown Mode Register16318.7.3 Shutdown Status Register16419. General Purpose Backup Registers (GPBR)16519.1 Description16519.2 Embedded Characteristics16519.3 General Purpose Backup Registers (GPBR) User Interface16619.3.1 General Purpose Backup Register x16620. Slow Clock Controller (SCKC)16720.1 Description16720.2 Embedded Characteristics16720.3 Block Diagram16720.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator16820.3.2 Bypass the 32768 Hz Oscillator16820.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator16820.4 Slow Clock Configuration (SCKC) User Interface16920.4.1 Slow Clock Configuration Register17021. Clock Generator (CKGR)17121.1 Description17121.2 Embedded Characteristics17121.3 CKGR Block Diagram17221.4 Slow Clock Selection17321.4.1 Switch from Internal 32 kHz RC Oscillator to the 32768 Hz Crystal17321.4.2 Bypass the 32768 Hz Oscillator17321.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator17421.4.4 Slow Clock Configuration Register17521.5 Main Clock17621.6 Main Clock Selection17721.6.1 Fast wake-up17721.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal17821.6.3 Bypass the 12 MHz Oscillator17821.6.4 Switch from the 12 MHz Crystal to Internal 12 MHz RC Oscillator17821.6.5 12 MHz Fast RC Oscillator17821.6.6 12 to 16 MHz Crystal Oscillator17821.6.7 Main Clock Oscillator Selection17921.6.8 Main Clock Frequency Counter17921.7 Divider and PLLA Block17921.7.1 Divider and Phase Lock Loop Programming18021.8 UTMI Phase Lock Loop Programming18022. Power Management Controller (PMC)18122.1 Description18122.2 Embedded Characteristics18122.3 Master Clock Controller18222.4 Block Diagram18322.5 Processor Clock Controller18322.6 USB Device and Host Clocks18422.7 LP-DDR/DDR2 Clock18422.8 Software Modem Clock18422.9 Peripheral Clock Controller18422.10 Programmable Clock Output Controller18522.11 Programming Sequence18522.12 Clock Switching Details18822.12.1 Master Clock Switching Timings18822.12.2 Clock Switching Waveforms18922.13 Power Management Controller (PMC) User Interface19122.13.1 PMC System Clock Enable Register19222.13.2 PMC System Clock Disable Register19322.13.3 PMC System Clock Status Register19422.13.4 PMC Peripheral Clock Enable Register19522.13.5 PMC Peripheral Clock Disable Register19622.13.6 PMC Peripheral Clock Status Register19722.13.7 PMC UTMI Clock Configuration Register19822.13.8 PMC Clock Generator Main Oscillator Register19922.13.9 PMC Clock Generator Main Clock Frequency Register20022.13.10 PMC Clock Generator PLLA Register20122.13.11 PMC Master Clock Register20222.13.12 PMC USB Clock Register20322.13.13 PMC SMD Clock Register20422.13.14 PMC Programmable Clock Register20522.13.15 PMC Interrupt Enable Register20622.13.16 PMC Interrupt Disable Register20722.13.17 PMC Status Register20822.13.18 PMC Interrupt Mask Register21022.13.19 PLL Charge Pump Current Register21122.13.20 PMC Write Protect Mode Register21222.13.21 PMC Write Protect Status Register21322.13.22 PMC Peripheral Control Register21423. Parallel Input/Output (PIO) Controller21523.1 Description21523.2 Embedded Characteristics21523.3 Block Diagram21623.4 Product Dependencies21723.4.1 Pin Multiplexing21723.4.2 External Interrupt Lines21723.4.3 Power Management21723.4.4 Interrupt Generation21723.5 Functional Description21823.5.1 Pull-up and Pull-down Resistor Control21923.5.2 I/O Line or Peripheral Function Selection21923.5.3 Peripheral A or B or C or D Selection21923.5.4 Output Control22023.5.5 Synchronous Data Output22023.5.6 Multi Drive Control (Open Drain)22023.5.7 Output Line Timings22023.5.8 Inputs22123.5.9 Input Glitch and Debouncing Filters22123.5.10 Input Edge/Level Interrupt22223.5.10.1 Example22323.5.10.2 Interrupt Mode Configuration22423.5.10.3 Edge or Level Detection Configuration22423.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration.22423.5.11 I/O Lines Lock22423.5.12 Programmable I/O Delays22423.5.13 Programmable I/O Drive22523.5.14 Programmable Schmitt Trigger22523.5.15 Write Protection Registers22523.6 I/O Lines Programming Example22723.7 Parallel Input/Output Controller (PIO) User Interface22823.7.1 PIO Enable Register23123.7.2 PIO Disable Register23123.7.3 PIO Status Register23223.7.4 PIO Output Enable Register23223.7.5 PIO Output Disable Register23323.7.6 PIO Output Status Register23323.7.7 PIO Input Filter Enable Register23423.7.8 PIO Input Filter Disable Register23423.7.9 PIO Input Filter Status Register23523.7.10 PIO Set Output Data Register23523.7.11 PIO Clear Output Data Register23623.7.12 PIO Output Data Status Register23623.7.13 PIO Pin Data Status Register23723.7.14 PIO Interrupt Enable Register23723.7.15 PIO Interrupt Disable Register23823.7.16 PIO Interrupt Mask Register23823.7.17 PIO Interrupt Status Register23923.7.18 PIO Multi-driver Enable Register23923.7.19 PIO Multi-driver Disable Register24023.7.20 PIO Multi-driver Status Register24023.7.21 PIO Pull Up Disable Register24123.7.22 PIO Pull Up Enable Register24123.7.23 PIO Pull Up Status Register24223.7.24 PIO Peripheral ABCD Select Register 124323.7.25 PIO Peripheral ABCD Select Register 224423.7.26 PIO Input Filter Slow Clock Disable Register24523.7.27 PIO Input Filter Slow Clock Enable Register24523.7.28 PIO Input Filter Slow Clock Status Register24623.7.29 PIO Slow Clock Divider Debouncing Register24623.7.30 PIO Pad Pull Down Disable Register24723.7.31 PIO Pad Pull Down Enable Register24723.7.32 PIO Pad Pull Down Status Register24823.7.33 PIO Output Write Enable Register24923.7.34 PIO Output Write Disable Register24923.7.35 PIO Output Write Status Register25023.7.36 PIO Additional Interrupt Modes Enable Register25023.7.37 PIO Additional Interrupt Modes Disable Register25123.7.38 PIO Additional Interrupt Modes Mask Register25123.7.39 PIO Edge Select Register25223.7.40 PIO Level Select Register25223.7.41 PIO Edge/Level Status Register25323.7.42 PIO Falling Edge/Low Level Select Register25323.7.43 PIO Rising Edge/High Level Select Register25423.7.44 PIO Fall/Rise - Low/High Status Register25423.7.45 PIO Lock Status Register25523.7.46 PIO Write Protect Mode Register25623.7.47 PIO Write Protect Status Register25723.7.48 PIO Schmitt Trigger Register25823.7.49 PIO I/O Delay Register25823.7.50 PIO I/O Drive Register 125923.7.51 PIO I/O Drive Register 226024. Debug Unit (DBGU)26124.1 Description26124.2 Embedded Characteristics26124.3 Block Diagram26224.4 Product Dependencies26324.4.1 I/O Lines26324.4.2 Power Management26324.4.3 Interrupt Source26324.5 UART Operations26324.5.1 Baud Rate Generator26324.5.2 Receiver26424.5.2.1 Receiver Reset, Enable and Disable26424.5.2.2 Start Detection and Data Sampling26424.5.2.3 Receiver Ready26524.5.2.4 Receiver Overrun26524.5.2.5 Parity Error26524.5.2.6 Receiver Framing Error26624.5.3 Transmitter26624.5.3.1 Transmitter Reset, Enable and Disable26624.5.3.2 Transmit Format26624.5.3.3 Transmitter Control26624.5.4 DMA Support26724.5.5 Test Modes26724.5.6 Debug Communication Channel Support26824.5.7 Chip Identifier26924.5.8 ICE Access Prevention26924.6 Debug Unit (DBGU) User Interface27024.6.1 Debug Unit Control Register27124.6.2 Debug Unit Mode Register27224.6.3 Debug Unit Interrupt Enable Register27324.6.4 Debug Unit Interrupt Disable Register27424.6.5 Debug Unit Interrupt Mask Register27524.6.6 Debug Unit Status Register27624.6.7 Debug Unit Receiver Holding Register27724.6.8 Debug Unit Transmit Holding Register27724.6.9 Debug Unit Baud Rate Generator Register27824.6.10 Debug Unit Chip ID Register27924.6.11 Debug Unit Chip ID Extension Register28324.6.12 Debug Unit Force NTRST Register28425. Bus Matrix (MATRIX)28525.1 Description28525.2 Embedded Characteristics28525.2.1 Matrix Masters28625.2.2 Matrix Slaves28625.2.3 Master to Slave Access28725.3 Memory Mapping28725.4 Special Bus Granting Mechanism28725.4.1 No Default Master28825.4.2 Last Access Master28825.4.3 Fixed Default Master28825.5 Arbitration28825.5.1 Arbitration Scheduling28825.5.1.1 Undefined Length Burst Arbitration28925.5.1.2 Slot Cycle Limit Arbitration28925.5.2 Arbitration Priority Scheme29025.5.2.1 Fixed Priority Arbitration29025.5.2.2 Round-Robin Arbitration29025.6 Write Protect Registers29025.7 Bus Matrix (MATRIX) User Interface29125.7.1 Bus Matrix Master Configuration Registers29325.7.2 Bus Matrix Slave Configuration Registers29425.7.3 Bus Matrix Priority Registers A For Slaves29525.7.4 Bus Matrix Priority Registers B For Slaves29625.7.5 Bus Matrix Master Remap Control Register29725.7.6 Chip Configuration User Interface29825.7.6.1 EBI Chip Select Assignment Register29925.7.7 Write Protect Mode Register30125.7.8 Write Protect Status Register30226. External Bus Interface (EBI)30326.1 Description30326.2 Embedded Characteristics30426.3 EBI Block Diagram30526.4 I/O Lines Description30626.5 Application Example30726.5.1 Hardware Interface30726.5.2 Product Dependencies30926.5.2.1 I/O Lines30926.5.3 Functional Description30926.5.3.1 Bus Multiplexing30926.5.3.2 Pull-up and Pull-down Control30926.5.3.3 Drive Level and Delay Control30926.5.3.4 Power supplies31126.5.3.5 Static Memory Controller31226.5.3.6 DDR2SDRAM Controller31226.5.3.7 Programmable Multibit ECC Controller31226.5.3.8 NAND Flash Support31226.5.4 Implementation Examples31426.5.4.1 2x8-bit DDR2 on EBI31426.5.4.2 16-bit LPDDR on EBI31526.5.4.3 16-bit SDRAM on EBI31626.5.4.4 2x16-bit SDRAM on EBI31726.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 031826.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 031926.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 132026.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 132126.5.4.9 NOR Flash on NCS032227. Programmable Multibit ECC Controller (PMECC)32327.1 Description32327.2 Embedded Characteristics32327.3 Block Diagram32427.4 Functional Description32527.4.1 MLC/SLC Write Page Operation using PMECC32727.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set32827.4.1.2 MLC/SLC Write Operation with Spare Area Disabled32827.4.2 MLC/SLC Read Page Operation using PMECC32927.4.2.1 MLC/SLC Read Operation with Spare Decoding32927.4.2.2 MLC/SLC Read Operation33027.4.2.3 MLC/SLC User Read ECC Area33027.5 Software Implementation33127.5.1 Remainder Substitution Procedure33127.5.2 Find the Error Location Polynomial Sigma(x)33127.5.3 Find the Error Position33427.6 Programmable Multibit ECC Controller (PMECC) User Interface33527.6.1 PMECC Configuration Register33727.6.2 PMECC Spare Area Size Register33927.6.3 PMECC Start Address Register34027.6.4 PMECC End Address Register34127.6.5 PMECC Clock Control Register34227.6.6 PMECC Control Register34327.6.7 PMECC Status Register34427.6.8 PMECC Interrupt Enable Register34527.6.9 PMECC Interrupt Disable Register34627.6.10 PMECC Interrupt Mask Register34727.6.11 PMECC Interrupt Status Register34827.6.12 PMECC ECC x Register34927.6.13 PMECC Remainder x Register35028. Programmable Multibit ECC Error Location Controller (PMERRLOC)35128.1 Description35128.2 Embedded Characteristics35128.3 Block Diagram35128.4 Functional Description35228.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface35328.5.1 Error Location Configuration Register35428.5.2 Error Location Primitive Register35528.5.3 Error Location Enable Register35628.5.4 Error Location Disable Register35728.5.5 Error Location Status Register35828.5.6 Error Location Interrupt Enable Register35928.5.7 Error Location Interrupt Disable Register36028.5.8 Error Location Interrupt Mask Register36128.5.9 Error Location Interrupt Status Register36228.5.10 Error Location SIGMAx Register36328.5.11 PMECC Error Locationx Register36429. Static Memory Controller (SMC)36529.1 Description36529.2 Embedded Characteristics36529.3 I/O Lines Description36629.4 Multiplexed Signals36629.5 Application Example36729.5.1 Hardware Interface36729.6 Product Dependencies36729.6.1 I/O Lines36729.7 External Memory Mapping36829.8 Connection to External Devices36829.8.1 Data Bus Width36829.8.2 Byte Write or Byte Select Access36829.8.2.1 Byte Write Access37029.8.2.2 Byte Select Access37029.8.2.3 Signal Multiplexing37129.9 Standard Read and Write Protocols37229.9.1 Read Waveforms37229.9.1.1 NRD Waveform37229.9.1.2 NCS Waveform37229.9.1.3 Read Cycle37329.9.1.4 Null Delay Setup and Hold37329.9.1.5 Null Pulse37429.9.2 Read Mode37429.9.2.1 Read is Controlled by NRD (READ_MODE = 1):37429.9.2.2 Read is Controlled by NCS (READ_MODE = 0)37429.9.3 Write Waveforms37529.9.3.1 NWE Waveforms37529.9.3.2 NCS Waveforms37529.9.3.3 Write Cycle37629.9.3.4 Null Delay Setup and Hold37629.9.3.5 Null Pulse37729.9.4 Write Mode37729.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)37729.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)37829.9.5 Write Protected Registers37829.9.6 Coding Timing Parameters37829.9.7 Reset Values of Timing Parameters37929.9.8 Usage Restriction37929.10 Automatic Wait States37929.10.1 Chip Select Wait States37929.10.2 Early Read Wait State38029.10.3 Reload User Configuration Wait State38229.10.3.1 User Procedure38229.10.3.2 Slow Clock Mode Transition38229.10.4 Read to Write Wait State38329.11 Data Float Wait States38329.11.1 READ_MODE38329.11.2 TDF Optimization Enabled (TDF_MODE = 1)38529.11.3 TDF Optimization Disabled (TDF_MODE = 0)38529.12 External Wait38729.12.1 Restriction38729.12.2 Frozen Mode38829.12.3 Ready Mode39029.12.4 NWAIT Latency and Read/Write Timings39229.13 Slow Clock Mode39329.13.1 Slow Clock Mode Waveforms39329.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode39429.14 Asynchronous Page Mode39629.14.1 Protocol and Timings in Page Mode39629.14.2 Byte Access Type in Page Mode39729.14.3 Page Mode Restriction39729.14.4 Sequential and Non-sequential Accesses39729.15 Programmable IO Delays39929.16 Static Memory Controller (SMC) User Interface40029.16.1 SMC Setup Register40129.16.2 SMC Pulse Register40229.16.3 SMC Cycle Register40329.16.4 SMC MODE Register40429.16.5 SMC DELAY I/O Register40629.16.6 SMC Write Protect Mode Register40729.16.7 SMC Write Protect Status Register40830. DDR SDR SDRAM Controller (DDRSDRC)40930.1 Description40930.2 Embedded Characteristics41030.3 DDRSDRC Module Diagram41130.4 Initialization Sequence41230.4.1 SDR-SDRAM Initialization41230.4.2 Low-power DDR1-SDRAM Initialization41230.4.3 DDR2-SDRAM Initialization41330.5 Functional Description41530.5.1 SDRAM Controller Write Cycle41530.5.2 SDRAM Controller Read Cycle42030.5.3 Refresh (Auto-refresh Command)42430.5.4 Power Management42430.5.4.1 Self Refresh Mode42430.5.4.2 Power-down Mode42730.5.4.3 Deep Power-down Mode42830.5.4.4 Reset Mode42930.5.5 Multi-port Functionality42930.5.6 Write Protected Registers43130.6 Software Interface/SDRAM Organization, Address Mapping43230.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks43230.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks43430.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width43430.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface43630.7.1 DDRSDRC Mode Register43730.7.2 DDRSDRC Refresh Timer Register43830.7.3 DDRSDRC Configuration Register43930.7.4 DDRSDRC Timing Parameter 0 Register44230.7.5 DDRSDRC Timing Parameter 1 Register44430.7.6 DDRSDRC Timing Parameter 2 Register44530.7.7 DDRSDRC Low-power Register44630.7.8 DDRSDRC Memory Device Register44830.7.9 DDRSDRC DLL Register44930.7.10 DDRSDRC High Speed Register45030.7.11 DDRSDRC Write Protect Mode Register45130.7.12 DDRSDRC Write Protect Status Register45231. DMA Controller (DMAC)45331.1 Description45331.2 Embedded Characteristics45331.2.1 DMA Controller 045431.2.2 DMA Controller 145531.3 Block Diagram45631.4 Functional Description45731.4.1 Basic Definitions45731.4.2 Memory Peripherals46031.4.3 Handshaking Interface46031.4.3.1 Software Handshaking46031.4.4 DMAC Transfer Types46131.4.4.1 Multi-buffer Transfers46131.4.4.2 Programming DMAC for Multiple Buffer Transfers46231.4.4.3 Ending Multi-buffer Transfers46331.4.5 Programming a Channel46331.4.5.1 Programming Examples46331.4.6 Disabling a Channel Prior to Transfer Completion47931.4.6.1 Abnormal Transfer Termination48031.5 DMAC Software Requirements48131.6 Write Protection Registers48231.7 DMA Controller (DMAC) User Interface48331.7.1 DMAC Global Configuration Register48431.7.2 DMAC Enable Register48531.7.3 DMAC Software Single Request Register48631.7.4 DMAC Software Chunk Transfer Request Register48731.7.5 DMAC Software Last Transfer Flag Register48831.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register48931.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register49031.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register49131.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register49231.7.10 DMAC Channel Handler Enable Register49331.7.11 DMAC Channel Handler Disable Register49431.7.12 DMAC Channel Handler Status Register49531.7.13 DMAC Channel x [x = 0..7] Source Address Register49631.7.14 DMAC Channel x [x = 0..7] Destination Address Register49731.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register49831.7.16 DMAC Channel x [x = 0..7] Control A Register49931.7.17 DMAC Channel x [x = 0..7] Control B Register50131.7.18 DMAC Channel x [x = 0..7] Configuration Register50331.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register50531.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register50631.7.21 DMAC Write Protect Mode Register50731.7.22 DMAC Write Protect Status Register50832. USB High Speed Device Port (UDPHS)50932.1 Description50932.2 Embedded Characteristics50932.3 Block Diagram51032.4 Typical Connection51132.5 Product Dependencies51132.5.1 Power Management51132.5.2 Interrupt51132.6 Functional Description51232.6.1 UTMI Transceivers Sharing51232.6.2 USB V2.0 High Speed Device Port Introduction51232.6.3 USB V2.0 High Speed Transfer Types51232.6.4 USB Transfer Event Definitions51332.6.5 USB V2.0 High Speed BUS Transactions51332.6.6 Endpoint Configuration51432.6.7 DPRAM Management51632.6.8 Transfer With DMA51832.6.9 Transfer Without DMA51832.6.10 Handling Transactions with USB V2.0 Device Peripheral51932.6.10.1 Setup Transaction51932.6.10.2 NYET51932.6.10.3 Data IN52032.6.10.4 Bulk IN or Interrupt IN52032.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)52032.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)52132.6.10.7 Isochronous IN52432.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example52432.6.10.9 Data OUT52532.6.10.10 Bulk OUT or Interrupt OUT52532.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)52532.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)52632.6.10.13 High Bandwidth Isochronous Endpoint OUT52732.6.10.14 Isochronous Endpoint Handling: OUT Example52832.6.10.15 STALL52832.6.11 Speed Identification52932.6.12 USB V2.0 High Speed Global Interrupt52932.6.13 Endpoint Interrupts52932.6.14 Power Modes53132.6.14.1 Controlling Device States53132.6.14.2 Not Powered State53232.6.14.3 Entering Attached State53232.6.14.4 From Powered State to Default State (Reset)53232.6.14.5 From Default State to Address State (Address Assigned)53232.6.14.6 From Address State to Configured State (Device Configured)53232.6.14.7 Entering Suspend State (Bus Activity)53232.6.14.8 Receiving a Host Resume53332.6.14.9 Sending an External Resume53332.6.15 Test Mode53332.7 USB High Speed Device Port (UDPHS) User Interface53432.7.1 UDPHS Control Register53532.7.2 UDPHS Frame Number Register53732.7.3 UDPHS Interrupt Enable Register53832.7.4 UDPHS Interrupt Status Register54032.7.5 UDPHS Clear Interrupt Register54232.7.6 UDPHS Endpoints Reset Register54332.7.7 UDPHS Test Register54432.7.8 UDPHS Endpoint Configuration Register54632.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)54832.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)55032.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)55232.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)55432.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)55632.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)55932.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)56232.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)56332.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)56432.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)56532.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)56632.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint)57032.7.21 UDPHS DMA Channel Transfer Descriptor57432.7.22 UDPHS DMA Next Descriptor Address Register57532.7.23 UDPHS DMA Channel Address Register57632.7.24 UDPHS DMA Channel Control Register57732.7.25 UDPHS DMA Channel Status Register57933. USB Host High Speed Port (UHPHS)58133.1 Description58133.2 Embedded Characteristics58133.3 Block Diagram58233.4 Typical Connection58333.5 Product Dependencies58433.5.1 I/O Lines58433.5.2 Power Management58433.5.3 Interrupt58533.6 Functional Description58533.6.1 UTMI transceivers Sharing58533.6.2 EHCI58633.6.3 OHCI58634. High Speed MultiMedia Card Interface (HSMCI)58734.1 Description58734.2 Embedded Characteristics58734.3 Block Diagram58834.4 Application Block Diagram58834.5 Pin Name List58934.6 Product Dependencies58934.6.1 I/O Lines58934.6.2 Power Management58934.6.3 Interrupt59034.7 Bus Topology59034.8 High Speed MultiMedia Card Operations59234.8.1 Command - Response Operation59234.8.2 Data Transfer Operation59534.8.3 Read Operation59534.8.4 Write Operation59734.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller59934.8.6 READ_SINGLE_BLOCK Operation using DMA Controller60034.8.6.1 Block Length is Multiple of 460034.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)60134.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)60334.8.7 WRITE_MULTIPLE_BLOCK60434.8.7.1 One Block per Descriptor60434.8.8 READ_MULTIPLE_BLOCK60534.8.8.1 Block Length is a Multiple of 460534.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)60634.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)60834.9 SD/SDIO Card Operation60934.9.1 SDIO Data Transfer Type60934.9.2 SDIO Interrupts61034.10 CE-ATA Operation61034.10.1 Executing an ATA Polling Command61034.10.2 Executing an ATA Interrupt Command61034.10.3 Aborting an ATA Command61034.10.4 CE-ATA Error Recovery61034.11 HSMCI Boot Operation Mode61134.11.1 Boot Procedure, Processor Mode61134.11.2 Boot Procedure DMA Mode61134.12 HSMCI Transfer Done Timings61234.12.1 Definition61234.12.2 Read Access61234.12.3 Write Access61234.13 Write Protection Registers61334.14 High Speed MultiMedia Card Interface (HSMCI) User Interface61434.14.1 HSMCI Control Register61534.14.2 HSMCI Mode Register61634.14.3 HSMCI Data Timeout Register61734.14.4 HSMCI SDCard/SDIO Register61834.14.5 HSMCI Argument Register61934.14.6 HSMCI Command Register62034.14.7 HSMCI Block Register62234.14.8 HSMCI Completion Signal Timeout Register62334.14.9 HSMCI Response Register62434.14.10 HSMCI Receive Data Register62534.14.11 HSMCI Transmit Data Register62634.14.12 HSMCI Status Register62734.14.13 HSMCI Interrupt Enable Register63034.14.14 HSMCI Interrupt Disable Register63234.14.15 HSMCI Interrupt Mask Register63434.14.16 HSMCI DMA Configuration Register63634.14.17 HSMCI Configuration Register63734.14.18 HSMCI Write Protect Mode Register63834.14.19 HSMCI Write Protect Status Register63934.14.20 HSMCI FIFOx Memory Aperture64035. Serial Peripheral Interface (SPI)64135.1 Description64135.2 Embedded Characteristics64135.3 Block Diagram64235.4 Application Block Diagram64235.5 Signal Description64335.6 Product Dependencies64335.6.1 I/O Lines64335.6.2 Power Management64335.6.3 Interrupt64435.6.4 Direct Memory Access Controller (DMAC)64435.7 Functional Description64435.7.1 Modes of Operation64435.7.2 Data Transfer64435.7.3 Master Mode Operations64635.7.3.1 Master Mode Block Diagram64735.7.3.2 Master Mode Flow Diagram64835.7.3.3 Clock Generation64935.7.3.4 Transfer Delays64935.7.3.5 Peripheral Selection65035.7.3.6 SPI Direct Access Memory Controller (DMAC)65035.7.3.7 Peripheral Chip Select Decoding65135.7.3.8 Peripheral Deselection without DMA65135.7.3.9 Peripheral Deselection with DMAC65235.7.3.10 Mode Fault Detection65335.7.4 SPI Slave Mode65335.7.5 Write Protected Registers65435.8 Serial Peripheral Interface (SPI) User Interface65535.8.1 SPI Control Register65635.8.2 SPI Mode Register65735.8.3 SPI Receive Data Register65935.8.4 SPI Transmit Data Register66035.8.5 SPI Status Register66135.8.6 SPI Interrupt Enable Register66235.8.7 SPI Interrupt Disable Register66335.8.8 SPI Interrupt Mask Register66435.8.9 SPI Chip Select Register66535.8.10 SPI Write Protection Mode Register66735.8.11 SPI Write Protection Status Register66836. Timer Counter (TC)66936.1 Description66936.2 Embedded Characteristics67036.3 Block Diagram67136.4 Pin Name List67236.5 Product Dependencies67236.5.1 I/O Lines67236.5.2 Power Management67236.5.3 Interrupt67236.6 Functional Description67336.6.1 TC Description67336.6.2 32-bit Counter67336.6.3 Clock Selection67336.6.4 Clock Control67536.6.5 TC Operating Modes67536.6.6 Trigger67636.6.7 Capture Operating Mode67636.6.8 Capture Registers A and B67636.6.9 Trigger Conditions67636.6.10 Waveform Operating Mode67836.6.11 Waveform Selection67836.6.11.1 WAVSEL = 0068036.6.11.2 WAVSEL = 1068136.6.11.3 WAVSEL = 0168236.6.11.4 WAVSEL = 1168336.6.12 External Event/Trigger Conditions68436.6.13 Output Controller68436.7 Timer Counter (TC) User Interface68536.7.1 TC Channel Control Register68636.7.2 TC Channel Mode Register: Capture Mode68736.7.3 TC Channel Mode Register: Waveform Mode68936.7.4 TC Counter Value Register69336.7.5 TC Register A69436.7.6 TC Register B69436.7.7 TC Register C69536.7.8 TC Status Register69636.7.9 TC Interrupt Enable Register69836.7.10 TC Interrupt Disable Register69936.7.11 TC Interrupt Mask Register70036.7.12 TC Block Control Register70136.7.13 TC Block Mode Register70237. Two-wire Interface (TWI)70337.1 Description70337.2 Embedded Characteristics70437.3 List of Abbreviations70437.4 Block Diagram70537.5 Application Block Diagram70537.5.1 I/O Lines Description70537.6 Product Dependencies70637.6.1 I/O Lines70637.6.2 Power Management70637.6.3 Interrupt70637.7 Functional Description70737.7.1 Transfer Format70737.7.2 Modes of Operation70737.8 Master Mode70837.8.1 Definition70837.8.2 Application Block Diagram70837.8.3 Programming Master Mode70837.8.4 Master Transmitter Mode70837.8.5 Master Receiver Mode71037.8.6 Internal Address71237.8.6.1 7-bit Slave Addressing71237.8.6.2 10-bit Slave Addressing71337.8.7 Using the DMA Controller71337.8.7.1 Data Transmit with the DMA71337.8.7.2 Data Receive with the DMA71337.8.8 SMBUS Quick Command (Master Mode Only)71437.8.9 Read-write Flowcharts71437.9 Multi-master Mode72137.9.1 Definition72137.9.2 Different Multi-master Modes72137.9.2.1 TWI as Master Only72137.9.2.2 TWI as Master or Slave72137.10 Slave Mode72437.10.1 Definition72437.10.2 Application Block Diagram72437.10.3 Programming Slave Mode72437.10.4 Receiving Data72437.10.4.1 Read Sequence72437.10.4.2 Write Sequence72537.10.4.3 Clock Synchronization Sequence72537.10.4.4 General Call72537.10.5 Data Transfer72537.10.5.1 Read Operation72537.10.5.2 Write Operation72637.10.5.3 General Call72637.10.5.4 Clock Synchronization72737.10.5.5 Reversal after a Repeated Start72937.10.6 Read Write Flowcharts73037.11 Write Protection System73137.12 Two-wire Interface (TWI) User Interface73237.12.1 TWI Control Register73337.12.2 TWI Master Mode Register73537.12.3 TWI Slave Mode Register73637.12.4 TWI Internal Address Register73737.12.5 TWI Clock Waveform Generator Register73837.12.6 TWI Status Register73937.12.7 TWI Interrupt Enable Register74237.12.8 TWI Interrupt Disable Register74337.12.9 TWI Interrupt Mask Register74437.12.10 TWI Receive Holding Register74537.12.11 TWI Transmit Holding Register74637.12.12 TWI Write Protection Mode Register74737.12.13 TWI Write Protection Status Register74838. Pulse Width Modulation Controller (PWM)74938.1 Description74938.2 Embedded characteristics74938.3 Block Diagram75038.4 I/O Lines Description75138.5 Product Dependencies75138.5.1 I/O Lines75138.5.2 Power Management75138.5.3 Interrupt Sources75138.6 Functional Description75238.6.1 PWM Clock Generator75238.6.2 PWM Channel75338.6.2.1 Block Diagram75338.6.2.2 Waveform Properties75338.6.3 PWM Controller Operations75638.6.3.1 Initialization75638.6.3.2 Source Clock Selection Criteria75638.6.3.3 Changing the Duty Cycle or the Period75638.6.3.4 Interrupts75738.7 Pulse Width Modulation Controller (PWM) User Interface75838.7.1 PWM Mode Register75938.7.2 PWM Enable Register76038.7.3 PWM Disable Register76038.7.4 PWM Status Register76138.7.5 PWM Interrupt Enable Register76238.7.6 PWM Interrupt Disable Register76338.7.7 PWM Interrupt Mask Register76438.7.8 PWM Interrupt Status Register76538.7.9 PWM Channel Mode Register76638.7.10 PWM Channel Duty Cycle Register76738.7.11 PWM Channel Period Register76838.7.12 PWM Channel Counter Register76938.7.13 PWM Channel Update Register77039. Universal Synchronous Asynchronous Receiver Transmitter (USART)77139.1 Description77139.2 Embedded Characteristics77239.3 Block Diagram77339.4 Application Block Diagram77439.5 I/O Lines Description77539.6 Product Dependencies77639.6.1 I/O Lines77639.6.2 Power Management77639.6.3 Interrupt77739.7 Functional Description77739.7.1 Baud Rate Generator77939.7.1.1 Baud Rate in Asynchronous Mode77939.7.1.2 Fractional Baud Rate in Asynchronous Mode78139.7.1.3 Baud Rate in Synchronous Mode or SPI Mode78139.7.1.4 Baud Rate in ISO 7816 Mode78239.7.2 Receiver and Transmitter Control78339.7.3 Synchronous and Asynchronous Modes78339.7.3.1 Transmitter Operations78339.7.3.2 Manchester Encoder78439.7.3.3 Asynchronous Receiver78639.7.3.4 Manchester Decoder78739.7.3.5 Radio Interface: Manchester Encoded USART Application78939.7.3.6 Synchronous Receiver79039.7.3.7 Receiver Operations79139.7.3.8 Parity79139.7.3.9 Multidrop Mode79239.7.3.10 Transmitter Timeguard79239.7.3.11 Receiver Time-out79339.7.3.12 Framing Error79539.7.3.13 Transmit Break79539.7.3.14 Receive Break79639.7.3.15 Hardware Handshaking79739.7.4 ISO7816 Mode79739.7.4.1 ISO7816 Mode Overview79739.7.4.2 Protocol T = 079839.7.4.3 Protocol T = 179939.7.5 IrDA Mode79939.7.5.1 IrDA Modulation80039.7.5.2 IrDA Baud Rate80139.7.5.3 IrDA Demodulator80139.7.6 RS485 Mode80239.7.7 SPI Mode80339.7.7.1 Modes of Operation80339.7.7.2 Baud Rate80439.7.7.3 Data Transfer80539.7.7.4 Receiver and Transmitter Control80639.7.7.5 Character Transmission80639.7.7.6 Character Reception80739.7.7.7 Receiver Timeout80739.7.8 LIN Mode80739.7.8.1 Modes of Operation80739.7.8.2 Baud Rate Configuration80739.7.8.3 Receiver and Transmitter Control80739.7.8.4 Character Transmission80739.7.8.5 Character Reception80739.7.8.6 Header Transmission (Master Node Configuration)80839.7.8.7 Header Reception (Slave Node Configuration)80839.7.8.8 Slave Node Synchronization80939.7.8.9 Identifier Parity81139.7.8.10 Node Action81139.7.8.11 Response Data Length81239.7.8.12 Checksum81239.7.8.13 Frame Slot Mode81339.7.8.14 LIN Errors81339.7.8.15 LIN Frame Handling81439.7.8.16 LIN Frame Handling With The DMAC81739.7.8.17 Wake-up Request81939.7.8.18 Bus Idle Time-out81939.7.9 Test Modes82039.7.9.1 Normal Mode82039.7.9.2 Automatic Echo Mode82039.7.9.3 Local Loopback Mode82039.7.9.4 Remote Loopback Mode82139.7.10 Write Protection Registers82239.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface82339.8.1 USART Control Register82439.8.2 USART Control Register (SPI_MODE)82639.8.3 USART Mode Register82839.8.4 USART Mode Register (SPI_MODE)83139.8.5 USART Interrupt Enable Register83339.8.6 USART Interrupt Enable Register (SPI_MODE)83439.8.7 USART Interrupt Enable Register (LIN_MODE)83539.8.8 USART Interrupt Disable Register83639.8.9 USART Interrupt Disable Register (SPI_MODE)83739.8.10 USART Interrupt Disable Register (LIN_MODE)83839.8.11 USART Interrupt Mask Register83939.8.12 USART Interrupt Mask Register (SPI_MODE)84039.8.13 USART Interrupt Mask Register (LIN_MODE)84139.8.14 USART Channel Status Register84239.8.15 USART Channel Status Register (SPI_MODE)84439.8.16 USART Channel Status Register (LIN_MODE)84539.8.17 USART Receive Holding Register84739.8.18 USART Transmit Holding Register84839.8.19 USART Baud Rate Generator Register84939.8.20 USART Receiver Time-out Register85039.8.21 USART Transmitter Timeguard Register85139.8.22 USART FI DI RATIO Register85239.8.23 USART Number of Errors Register85339.8.24 USART IrDA FILTER Register85439.8.25 USART Manchester Configuration Register85539.8.26 USART LIN Mode Register85739.8.27 USART LIN Identifier Register85939.8.28 USART LIN Baud Rate Register86039.8.29 USART Write Protect Mode Register86139.8.30 USART Write Protect Status Register86240. Analog-to-Digital Converter (ADC)86340.1 Description86340.2 Embedded Characteristics86440.3 Block Diagram86540.4 Signal Description86540.5 Product Dependencies86640.5.1 Power Management86640.5.2 Interrupt Sources86640.5.3 Analog Inputs86640.5.4 I/O Lines86640.5.5 Timer Triggers86640.5.6 Conversion Performances86640.6 Functional Description86740.6.1 Analog-to-digital Conversion86740.6.2 Conversion Reference86740.6.3 Conversion Resolution86740.6.4 Conversion Results86840.6.5 Conversion Triggers86940.6.6 Sleep Mode and Conversion Sequencer87040.6.7 Comparison Window87040.6.8 ADC Timings87140.6.9 Buffer Structure87140.6.10 Write Protected Registers87140.7 Analog-to-Digital Converter (ADC) User Interface87240.7.1 ADC Control Register87340.7.2 ADC Mode Register87440.7.3 ADC Channel Sequence 1 Register87640.7.4 ADC Channel Sequence 2 Register87740.7.5 ADC Channel Enable Register87840.7.6 ADC Channel Disable Register87940.7.7 ADC Channel Status Register88040.7.8 ADC Last Converted Data Register88140.7.9 ADC Interrupt Enable Register88240.7.10 ADC Interrupt Disable Register88340.7.11 ADC Interrupt Mask Register88440.7.12 ADC Interrupt Status Register88540.7.13 ADC Overrun Status Register88640.7.14 ADC Extended Mode Register88740.7.15 ADC Compare Window Register88840.7.16 ADC Channel Data Register88940.7.17 ADC Trigger Register89040.7.18 ADC Write Protect Mode Register89140.7.19 ADC Write Protect Status Register89241. Universal Asynchronous Receiver Transmitter (UART)89341.1 Description89341.2 Embedded Characteristics89341.3 Block Diagram89441.4 Product Dependencies89541.4.1 I/O Lines89541.4.2 Power Management89541.4.3 Interrupt Source89541.5 UART Operations89541.5.1 Baud Rate Generator89541.5.2 Receiver89641.5.2.1 Receiver Reset, Enable and Disable89641.5.2.2 Start Detection and Data Sampling89641.5.2.3 Receiver Ready89741.5.2.4 Receiver Overrun89741.5.2.5 Parity Error89741.5.2.6 Receiver Framing Error89841.5.3 Transmitter89841.5.3.1 Transmitter Reset, Enable and Disable89841.5.3.2 Transmit Format89841.5.3.3 Transmitter Control89941.5.4 DMA Support89941.5.5 Test Modes89941.6 Universal Asynchronous Receiver Transmitter (UART) User Interface90141.6.1 UART Control Register90241.6.2 UART Mode Register90341.6.3 UART Interrupt Enable Register90441.6.4 UART Interrupt Disable Register90541.6.5 UART Interrupt Mask Register90641.6.6 UART Status Register90741.6.7 UART Receiver Holding Register90841.6.8 UART Transmit Holding Register90941.6.9 UART Baud Rate Generator Register91042. Software Modem Device (SMD)91142.1 Description91142.2 Embedded Characteristics91142.3 Block Diagram91243. Synchronous Serial Controller (SSC)91343.1 Description91343.2 Embedded Characteristics91343.3 Block Diagram91443.4 Application Block Diagram91443.5 Pin Name List91543.6 Product Dependencies91543.6.1 I/O Lines91543.6.2 Power Management91543.6.3 Interrupt91543.7 Functional Description91643.7.1 Clock Management91743.7.1.1 Clock Divider91743.7.1.2 Transmitter Clock Management91843.7.1.3 Receiver Clock Management91843.7.1.4 Serial Clock Ratio Considerations91943.7.2 Transmitter Operations91943.7.3 Receiver Operations92043.7.4 Start92143.7.5 Frame Sync92343.7.5.1 Frame Sync Data92343.7.5.2 Frame Sync Edge Detection92343.7.6 Receive Compare Modes92343.7.6.1 Compare Functions92343.7.7 Data Format92443.7.8 Loop Mode92543.7.9 Interrupt92543.8 SSC Application Examples92743.8.1 Write Protection Registers92943.9 Synchronous Serial Controller (SSC) User Interface93043.9.1 SSC Control Register93143.9.2 SSC Clock Mode Register93243.9.3 SSC Receive Clock Mode Register93343.9.4 SSC Receive Frame Mode Register93543.9.5 SSC Transmit Clock Mode Register93743.9.6 SSC Transmit Frame Mode Register93943.9.7 SSC Receive Holding Register94143.9.8 SSC Transmit Holding Register94143.9.9 SSC Receive Synchronization Holding Register94243.9.10 SSC Transmit Synchronization Holding Register94243.9.11 SSC Receive Compare 0 Register94343.9.12 SSC Receive Compare 1 Register94343.9.13 SSC Status Register94443.9.14 SSC Interrupt Enable Register94643.9.15 SSC Interrupt Disable Register94743.9.16 SSC Interrupt Mask Register94843.9.17 SSC Write Protect Mode Register94943.9.18 SSC Write Protect Status Register95044. Image Sensor Interface (ISI)95144.1 Description95144.2 Embedded Characteristics95244.3 Block Diagram95344.4 Functional Description95444.4.1 Data Timing95444.4.2 Data Ordering95544.4.3 Clocks95644.4.4 Preview Path95744.4.4.1 Scaling, Decimation (Subsampling)95744.4.4.2 Color Space Conversion95844.4.4.3 Memory Interface95944.4.4.4 FIFO and DMA Features95944.4.5 Codec Path96044.4.5.1 Color Space Conversion96044.4.5.2 Memory Interface96044.4.5.3 DMA Features96044.5 Image Sensor Interface (ISI) User Interface96144.5.1 ISI Configuration 1 Register96244.5.2 ISI Configuration 2 Register96444.5.3 ISI Preview Register96644.5.4 ISI Preview Decimation Factor Register96744.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register96844.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register96944.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register97044.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register97144.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register97244.5.10 ISI Control Register97344.5.11 ISI Status Register97444.5.12 ISI Interrupt Enable Register97644.5.13 ISI Interrupt Disable Register97744.5.14 ISI Interrupt Mask Register97844.5.15 DMA Channel Enable Register98044.5.16 DMA Channel Disable Register98144.5.17 DMA Channel Status Register98244.5.18 DMA Preview Base Address Register98344.5.19 DMA Preview Control Register98444.5.20 DMA Preview Descriptor Address Register98544.5.21 DMA Codec Base Address Register98644.5.22 DMA Codec Control Register98744.5.23 DMA Codec Descriptor Address Register98844.5.24 ISI Write Protection Control98944.5.25 ISI Write Protection Status99045. Ethernet MAC 10/100 (EMAC)99145.1 Description99145.2 Embedded Characteristics99145.3 Block Diagram99245.4 Functional Description99345.4.1 Clock99345.4.2 Memory Interface99345.4.2.1 FIFO99345.4.2.2 Receive Buffers99445.4.2.3 Transmit Buffer99645.4.3 Transmit Block99745.4.4 Pause Frame Support99845.4.5 Receive Block99845.4.6 Address Checking Block99845.4.7 Broadcast Address99945.4.8 Hash Addressing99945.4.9 Copy All Frames (or Promiscuous Mode)100045.4.10 Type ID Checking100045.4.11 VLAN Support100045.4.12 PHY Maintenance100145.4.13 Physical Interface100145.4.13.1 RMII Transmit and Receive Operation100145.5 Programming Interface100245.5.1 Initialization100245.5.1.1 Configuration100245.5.1.2 Receive Buffer List100245.5.1.3 Transmit Buffer List100245.5.1.4 Address Matching100345.5.1.5 Interrupts100345.5.1.6 Transmitting Frames100345.5.1.7 Receiving Frames100345.6 Ethernet MAC 10/100 (EMAC) User Interface100545.6.1 Network Control Register100745.6.2 Network Configuration Register100945.6.3 Network Status Register101145.6.4 Transmit Status Register101245.6.5 Receive Buffer Queue Pointer Register101345.6.6 Transmit Buffer Queue Pointer Register101445.6.7 Receive Status Register101545.6.8 Interrupt Status Register101645.6.9 Interrupt Enable Register101745.6.10 Interrupt Disable Register101945.6.11 Interrupt Mask Register102045.6.12 PHY Maintenance Register102145.6.13 Pause Time Register102245.6.14 Hash Register Bottom102345.6.15 Hash Register Top102345.6.16 Specific Address 1 Bottom Register102445.6.17 Specific Address 1 Top Register102445.6.18 Specific Address 2 Bottom Register102545.6.19 Specific Address 2 Top Register102545.6.20 Specific Address 3 Bottom Register102645.6.21 Specific Address 3 Top Register102645.6.22 Specific Address 4 Bottom Register102745.6.23 Specific Address 4 Top Register102745.6.24 Type ID Checking Register102845.6.25 User Input/Output Register102945.6.26 EMAC Statistic Registers103045.6.26.1 Pause Frames Received Register103045.6.26.2 Frames Transmitted OK Register103045.6.26.3 Single Collision Frames Register103145.6.26.4 Multicollision Frames Register103145.6.26.5 Frames Received OK Register103245.6.26.6 Frames Check Sequence Errors Register103245.6.26.7 Alignment Errors Register103345.6.26.8 Deferred Transmission Frames Register103345.6.26.9 Late Collisions Register103445.6.26.10 Excessive Collisions Register103445.6.26.11 Transmit Underrun Errors Register103545.6.26.12 Carrier Sense Errors Register103545.6.26.13 Receive Resource Errors Register103645.6.26.14 Receive Overrun Errors Register103645.6.26.15 Receive Symbol Errors Register103745.6.26.16 Excessive Length Errors Register103745.6.26.17 Receive Jabbers Register103845.6.26.18 Undersize Frames Register103845.6.26.19 SQE Test Errors Register103945.6.26.20 Received Length Field Mismatch Register104046. Electrical Characteristics104146.1 Absolute Maximum Ratings104146.2 DC Characteristics104146.3 Power Consumption104346.3.1 Power Consumption versus Modes104346.4 Clock Characteristics104546.4.1 Processor Clock Characteristics104546.4.2 Master Clock Characteristics104546.5 Main Oscillator Characteristics104646.5.1 Crystal Oscillator Characteristics104746.5.2 XIN Clock Characteristics104746.6 12 MHz RC Oscillator Characteristics104846.7 32 kHz Oscillator Characteristics104846.7.1 32 kHz Crystal Characteristics104946.7.2 XIN32 Clock Characteristics104946.8 32 kHz RC Oscillator Characteristics105046.9 PLL Characteristics105046.9.1 UTMI PLL Characteristics105146.10 I/Os105146.11 USB HS Characteristics105146.11.1 Electrical Characteristics105146.11.2 Static Power Consumption105246.11.3 Dynamic Power Consumption105246.12 USB Transceiver Characteristics105346.12.1 Electrical Characteristics105346.13 Analog-to-Digital Converter (ADC)105446.14 Core Power Supply POR Characteristics105546.14.1 Power Sequence Requirements105546.14.2 Power-Up Sequence105646.15 SMC Timings105746.15.1 Timing Conditions105746.15.2 Timing Extraction105746.15.2.1 Zero Hold Mode Restrictions105746.15.2.2 Read Timings105746.15.2.3 Write Timings105846.16 DDRSDRC Timings106146.17 Peripheral Timings106146.17.1 SPI106146.17.1.1 Maximum SPI Frequency106146.17.1.2 Timing Conditions106146.17.1.3 Timing Extraction106246.17.2 SSC106546.17.2.1 Timing conditions106546.17.2.2 Timing Extraction106546.17.3 ISI106946.17.3.1 Timing conditions106946.17.3.2 Timing Extraction107046.17.4 HSMCI107046.17.5 EMAC107046.17.5.1 Timing conditions107046.17.5.2 Timing constraints107146.17.5.3 MII Mode107146.17.6 USART in SPI Mode Timings107346.17.6.1 Timing conditions107346.17.6.2 Timing extraction107347. Mechanical Overview107647.1 217-ball BGA Package107647.2 247-ball BGA Packages107847.2.1 247-ball TFBGA package107847.2.2 247-ball VFBGA package108047.3 Marking108148. SAM9G25 Ordering Information108249. SAM9G25 Errata108349.1 External Bus Interface (EBI)108349.1.1 EBI: Data lines are Hi-Z after reset108349.2 Reset Controller (RSTC)108349.2.1 RSTC: Reset during SDRAM Accesses108349.3 Static Memory Controller (SMC)108349.3.1 SMC: SMC DELAY I/O Registers are write-only108349.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)108349.4.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL108349.5 Timer Counter (TC)108449.5.1 TC: The TIOA5 signal is not well connected1084Revision History1085Table of Contents1094サイズ： 5.84MBページ数： 1102Language: Englishマニュアルを開く
データシート (AT91SAM9G25-EK)目次Description11. Features22. Block Diagram43. Signal Description54. Package and Pinout94.1 Overview of the 217-ball BGA Package94.2 Overview of the 247-ball BGA Packages104.2.1 247-ball TFBGA Package104.2.2 247-ball VFBGA Package104.3 I/O Description114.3.1 Reset State124.4 217-ball BGA Package Pinout134.5 247-ball BGA Package Pinout195. Power Considerations265.1 Power Supplies266. Memories276.1 Memory Mapping286.2 Embedded Memories286.2.1 Internal SRAM286.2.2 Internal ROM286.3 External Memories286.3.1 External Bus Interface286.3.2 Static Memory Controller286.3.3 DDR2SDR Controller297. System Controller307.1 Chip Identification327.2 Backup Section328. Peripherals338.1 Peripheral Mapping338.2 Peripheral Identifiers338.3 Peripheral Signal Multiplexing on I/O Lines349. ARM926EJ-S™359.1 Description359.2 Embedded Characteristics359.3 Block Diagram379.4 ARM9EJ-S Processor389.4.1 ARM9EJ-S Operating States389.4.2 Switching State389.4.3 Instruction Pipelines389.4.4 Memory Access389.4.5 Jazelle Technology389.4.6 ARM9EJ-S Operating Modes399.4.7 ARM9EJ-S Registers399.4.7.1 Status Registers409.4.7.2 Exceptions419.4.8 ARM Instruction Set Overview429.4.9 New ARM Instruction Set439.4.10 Thumb Instruction Set Overview449.5 CP15 Coprocessor459.5.1 CP15 Registers Access469.6 Memory Management Unit (MMU)479.6.1 Access Control Logic479.6.2 Translation Look-aside Buffer (TLB)479.6.3 Translation Table Walk Hardware489.6.4 MMU Faults489.7 Caches and Write Buffer489.7.1 Instruction Cache (ICache)489.7.2 Data Cache (DCache) and Write Buffer499.7.2.1 DCache499.7.2.2 Write Buffer499.8 Bus Interface Unit509.8.1 Supported Transfers509.8.2 Thumb Instruction Fetches509.8.3 Address Alignment5010. Debug and Test5110.1 Description5110.2 Embedded Characteristics5110.3 Block Diagram5210.4 Application Examples5310.4.1 Debug Environment5310.4.2 Test Environment5410.5 Debug and Test Pin Description5510.6 Functional Description5610.6.1 Test Pin5610.6.2 EmbeddedICE™5610.6.3 JTAG Signal Description5610.6.4 Debug Unit5610.6.5 IEEE 1149.1 JTAG Boundary Scan5710.6.6 JTAG ID Code Register5811. Boot Strategies5911.1 ROM Code5911.2 Flow Diagram5911.3 Chip Setup6011.4 NVM Boot6011.4.1 NVM Boot Sequence6011.4.2 NVM Bootloader Program Description6211.4.3 Valid Code Detection6311.4.3.1 ARM Exception Vectors Check6311.4.3.2 boot.bin File Check6411.4.4 Detailed Memory Boot Procedures6411.4.4.1 NAND Flash Boot: NAND Flash Detection6411.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction6711.4.4.3 SD Card Boot6911.4.4.4 SPI Flash Boot6911.4.4.5 TWI EEPROM Boot6911.4.5 Hardware and Software Constraints6911.5 SAM-BA Monitor7111.5.1 Command List7111.5.2 DBGU Serial Port7211.5.2.1 Supported External Crystal/External Clocks7211.5.2.2 Xmodem Protocol7211.5.3 USB Device Port7311.5.3.1 Supported External Crystal / External Clocks7311.5.3.2 USB Class7311.5.3.3 Enumeration Process7311.5.3.4 Communication Endpoints7412. Boot Sequence Controller (BSC)7512.1 Description7512.2 Embedded Characteristics7512.3 Product Dependencies7512.4 Boot Sequence Controller (BSC) User Interface7612.4.1 Boot Sequence Configuration Register7713. Advanced Interrupt Controller (AIC)7813.1 Description7813.2 Embedded Characteristics7813.3 Block Diagram7913.4 Application Block Diagram7913.5 AIC Detailed Block Diagram7913.6 I/O Line Description8013.7 Product Dependencies8013.7.1 I/O Lines8013.7.2 Power Management8013.7.3 Interrupt Sources8013.8 Functional Description8113.8.1 Interrupt Source Control8113.8.1.1 Interrupt Source Mode8113.8.1.2 Interrupt Source Enabling8113.8.1.3 Interrupt Clearing and Setting8113.8.1.4 Interrupt Status8113.8.2 Interrupt Latencies8313.8.3 Normal Interrupt8413.8.3.1 Priority Controller8413.8.3.2 Interrupt Nesting8413.8.3.3 Interrupt Vectoring8513.8.3.4 Interrupt Handlers8513.8.4 Fast Interrupt8613.8.4.1 Fast Interrupt Source8613.8.4.2 Fast Interrupt Control8613.8.4.3 Fast Interrupt Vectoring8613.8.4.4 Fast Interrupt Handlers8713.8.4.5 Fast Forcing8713.8.5 Protect Mode8813.8.6 Spurious Interrupt8913.8.7 General Interrupt Mask8913.9 Write Protection Registers9013.10 Advanced Interrupt Controller (AIC) User Interface9113.10.1 Base Address9113.10.2 AIC Source Mode Register9213.10.3 AIC Source Vector Register9313.10.4 AIC Interrupt Vector Register9413.10.5 AIC FIQ Vector Register9513.10.6 AIC Interrupt Status Register9613.10.7 AIC Interrupt Pending Register9713.10.8 AIC Interrupt Mask Register9813.10.9 AIC Core Interrupt Status Register9913.10.10 AIC Interrupt Enable Command Register10013.10.11 AIC Interrupt Disable Command Register10113.10.12 AIC Interrupt Clear Command Register10213.10.13 AIC Interrupt Set Command Register10313.10.14 AIC End of Interrupt Command Register10413.10.15 AIC Spurious Interrupt Vector Register10513.10.16 AIC Debug Control Register10613.10.17 AIC Fast Forcing Enable Register10713.10.18 AIC Fast Forcing Disable Register10813.10.19 AIC Fast Forcing Status Register10913.10.20 AIC Write Protect Mode Register11013.10.21 AIC Write Protect Status Register11114. Reset Controller (RSTC)11214.1 Description11214.2 Embedded Characteristics11214.3 Block Diagram11314.4 Functional Description11414.4.1 Reset Controller Overview11414.4.2 NRST Manager11414.4.2.1 NRST Signal11414.4.2.2 NRST External Reset Control11514.4.3 BMS Sampling11514.4.4 Reset States11514.4.4.1 General Reset11514.4.4.2 Wake-up Reset11614.4.4.3 User Reset11714.4.4.4 Software Reset11814.4.4.5 Watchdog Reset11914.4.5 Reset State Priorities12014.4.6 Reset Controller Status Register12114.5 Reset Controller (RSTC) User Interface12214.5.1 Reset Controller Control Register12314.5.2 Reset Controller Status Register12414.5.3 Reset Controller Mode Register12515. Real-time Clock (RTC)12615.1 Description12615.2 Embedded Characteristics12615.3 Block Diagram12715.4 Product Dependencies12815.4.1 Power Management12815.4.2 Interrupt12815.5 Functional Description12815.5.1 Reference Clock12815.5.2 Timing12815.5.3 Alarm12815.5.4 Error Checking when Programming12915.5.5 Updating Time/Calendar12915.6 Real-time Clock (RTC) User Interface13115.6.1 RTC Control Register13215.6.2 RTC Mode Register13315.6.3 RTC Time Register13415.6.4 RTC Calendar Register13515.6.5 RTC Time Alarm Register13615.6.6 RTC Calendar Alarm Register13715.6.7 RTC Status Register13815.6.8 RTC Status Clear Command Register13915.6.9 RTC Interrupt Enable Register14015.6.10 RTC Interrupt Disable Register14115.6.11 RTC Interrupt Mask Register14215.6.12 RTC Valid Entry Register14316. Periodic Interval Timer (PIT)14416.1 Description14416.2 Embedded Characteristics14416.3 Block Diagram14516.4 Functional Description14616.5 Periodic Interval Timer (PIT) User Interface14716.5.1 Periodic Interval Timer Mode Register14816.5.2 Periodic Interval Timer Status Register14916.5.3 Periodic Interval Timer Value Register15016.5.4 Periodic Interval Timer Image Register15117. Watchdog Timer (WDT)15217.1 Description15217.2 Embedded Characteristics15217.3 Block Diagram15317.4 Functional Description15417.5 Watchdog Timer (WDT) User Interface15617.5.1 Watchdog Timer Control Register15717.5.2 Watchdog Timer Mode Register15817.5.3 Watchdog Timer Status Register16018. Shutdown Controller (SHDWC)16118.1 Description16118.2 Embedded Characteristics16118.3 Block Diagram16118.4 I/O Lines Description16218.5 Product Dependencies16218.5.1 Power Management16218.6 Functional Description16218.7 Shutdown Controller (SHDWC) User Interface16318.7.1 Shutdown Control Register16418.7.2 Shutdown Mode Register16518.7.3 Shutdown Status Register16619. General Purpose Backup Registers (GPBR)16719.1 Description16719.2 Embedded Characteristics16719.3 General Purpose Backup Registers (GPBR) User Interface16819.3.1 General Purpose Backup Register x16920. Slow Clock Controller (SCKC)17020.1 Description17020.2 Embedded Characteristics17020.3 Block Diagram17020.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator17120.3.2 Bypass the 32768 Hz Oscillator17120.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator17120.4 Slow Clock Configuration (SCKC) User Interface17220.4.1 Slow Clock Configuration Register17321. Clock Generator (CKGR)17421.1 Description17421.2 Embedded Characteristics17421.3 CKGR Block Diagram17521.4 Slow Clock Selection17621.4.1 Switch from Internal 32 kHz RC Oscillator to the 32768 Hz Crystal17621.4.2 Bypass the 32768 Hz Oscillator17621.4.3 Switch from the 32768 Hz Crystal to Internal 32 kHz RC Oscillator17721.4.4 Slow Clock Configuration Register17821.5 Main Clock17921.6 Main Clock Selection18021.6.1 Fast wake-up18021.6.2 Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal18121.6.3 Bypass the 12 MHz Oscillator18121.6.4 Switch from the 12 MHz Crystal to Internal 12 MHz RC Oscillator18121.6.5 12 MHz Fast RC Oscillator18121.6.6 12 to 16 MHz Crystal Oscillator18121.6.7 Main Clock Oscillator Selection18221.6.8 Main Clock Frequency Counter18221.7 Divider and PLLA Block18221.7.1 Divider and Phase Lock Loop Programming18321.8 UTMI Phase Lock Loop Programming18322. Power Management Controller (PMC)18422.1 Description18422.2 Embedded Characteristics18422.3 Master Clock Controller18522.4 Block Diagram18622.5 Processor Clock Controller18622.6 USB Device and Host Clocks18722.7 LP-DDR/DDR2 Clock18722.8 Software Modem Clock18722.9 Peripheral Clock Controller18722.10 Programmable Clock Output Controller18822.11 Programming Sequence18822.12 Clock Switching Details19122.12.1 Master Clock Switching Timings19122.12.2 Clock Switching Waveforms19222.13 Power Management Controller (PMC) User Interface19422.13.1 PMC System Clock Enable Register19522.13.2 PMC System Clock Disable Register19622.13.3 PMC System Clock Status Register19722.13.4 PMC Peripheral Clock Enable Register19822.13.5 PMC Peripheral Clock Disable Register19922.13.6 PMC Peripheral Clock Status Register20022.13.7 PMC UTMI Clock Configuration Register20122.13.8 PMC Clock Generator Main Oscillator Register20222.13.9 PMC Clock Generator Main Clock Frequency Register20322.13.10 PMC Clock Generator PLLA Register20422.13.11 PMC Master Clock Register20522.13.12 PMC USB Clock Register20722.13.13 PMC SMD Clock Register20822.13.14 PMC Programmable Clock Register20922.13.15 PMC Interrupt Enable Register21022.13.16 PMC Interrupt Disable Register21122.13.17 PMC Status Register21222.13.18 PMC Interrupt Mask Register21422.13.19 PLL Charge Pump Current Register21522.13.20 PMC Write Protect Mode Register21622.13.21 PMC Write Protect Status Register21722.13.22 PMC Peripheral Control Register21823. Parallel Input/Output (PIO) Controller21923.1 Description21923.2 Embedded Characteristics21923.3 Block Diagram22023.4 Product Dependencies22123.4.1 Pin Multiplexing22123.4.2 External Interrupt Lines22123.4.3 Power Management22123.4.4 Interrupt Generation22123.5 Functional Description22223.5.1 Pull-up and Pull-down Resistor Control22323.5.2 I/O Line or Peripheral Function Selection22323.5.3 Peripheral A or B or C or D Selection22323.5.4 Output Control22423.5.5 Synchronous Data Output22423.5.6 Multi Drive Control (Open Drain)22423.5.7 Output Line Timings22423.5.8 Inputs22523.5.9 Input Glitch and Debouncing Filters22523.5.10 Input Edge/Level Interrupt22623.5.10.1 Example22723.5.10.2 Interrupt Mode Configuration22823.5.10.3 Edge or Level Detection Configuration22823.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration.22823.5.11 I/O Lines Lock22823.5.12 Programmable I/O Delays22823.5.13 Programmable I/O Drive22923.5.14 Programmable Schmitt Trigger22923.5.15 Write Protection Registers23023.6 I/O Lines Programming Example23123.7 Parallel Input/Output Controller (PIO) User Interface23223.7.1 PIO Enable Register23523.7.2 PIO Disable Register23623.7.3 PIO Status Register23723.7.4 PIO Output Enable Register23823.7.5 PIO Output Disable Register23923.7.6 PIO Output Status Register24023.7.7 PIO Input Filter Enable Register24123.7.8 PIO Input Filter Disable Register24223.7.9 PIO Input Filter Status Register24323.7.10 PIO Set Output Data Register24423.7.11 PIO Clear Output Data Register24523.7.12 PIO Output Data Status Register24623.7.13 PIO Pin Data Status Register24723.7.14 PIO Interrupt Enable Register24823.7.15 PIO Interrupt Disable Register24923.7.16 PIO Interrupt Mask Register25023.7.17 PIO Interrupt Status Register25123.7.18 PIO Multi-driver Enable Register25223.7.19 PIO Multi-driver Disable Register25323.7.20 PIO Multi-driver Status Register25423.7.21 PIO Pull Up Disable Register25523.7.22 PIO Pull Up Enable Register25623.7.23 PIO Pull Up Status Register25723.7.24 PIO Peripheral ABCD Select Register 125823.7.25 PIO Peripheral ABCD Select Register 225923.7.26 PIO Input Filter Slow Clock Disable Register26023.7.27 PIO Input Filter Slow Clock Enable Register26123.7.28 PIO Input Filter Slow Clock Status Register26223.7.29 PIO Slow Clock Divider Debouncing Register26323.7.30 PIO Pad Pull Down Disable Register26423.7.31 PIO Pad Pull Down Enable Register26523.7.32 PIO Pad Pull Down Status Register26623.7.33 PIO Output Write Enable Register26723.7.34 PIO Output Write Disable Register26823.7.35 PIO Output Write Status Register26923.7.36 PIO Additional Interrupt Modes Enable Register27023.7.37 PIO Additional Interrupt Modes Disable Register27123.7.38 PIO Additional Interrupt Modes Mask Register27223.7.39 PIO Edge Select Register27323.7.40 PIO Level Select Register27423.7.41 PIO Edge/Level Status Register27523.7.42 PIO Falling Edge/Low Level Select Register27623.7.43 PIO Rising Edge/High Level Select Register27723.7.44 PIO Fall/Rise - Low/High Status Register27823.7.45 PIO Lock Status Register27923.7.46 PIO Write Protect Mode Register28023.7.47 PIO Write Protect Status Register28123.7.48 PIO Schmitt Trigger Register28223.7.49 PIO I/O Delay Register28323.7.50 PIO I/O Drive Register 128423.7.51 PIO I/O Drive Register 228524. Debug Unit (DBGU)28624.1 Description28624.2 Embedded Characteristics28624.3 Block Diagram28724.4 Product Dependencies28824.4.1 I/O Lines28824.4.2 Power Management28824.4.3 Interrupt Source28824.5 UART Operations28824.5.1 Baud Rate Generator28824.5.2 Receiver28924.5.2.1 Receiver Reset, Enable and Disable28924.5.2.2 Start Detection and Data Sampling28924.5.2.3 Receiver Ready29024.5.2.4 Receiver Overrun29024.5.2.5 Parity Error29024.5.2.6 Receiver Framing Error29124.5.3 Transmitter29124.5.3.1 Transmitter Reset, Enable and Disable29124.5.3.2 Transmit Format29124.5.3.3 Transmitter Control29124.5.4 DMA Support29224.5.5 Test Modes29224.5.6 Debug Communication Channel Support29324.5.7 Chip Identifier29424.5.8 ICE Access Prevention29424.6 Debug Unit (DBGU) User Interface29524.6.1 Debug Unit Control Register29624.6.2 Debug Unit Mode Register29724.6.3 Debug Unit Interrupt Enable Register29824.6.4 Debug Unit Interrupt Disable Register29924.6.5 Debug Unit Interrupt Mask Register30024.6.6 Debug Unit Status Register30124.6.7 Debug Unit Receiver Holding Register30224.6.8 Debug Unit Transmit Holding Register30324.6.9 Debug Unit Baud Rate Generator Register30424.6.10 Debug Unit Chip ID Register30524.6.11 Debug Unit Chip ID Extension Register30924.6.12 Debug Unit Force NTRST Register31025. Bus Matrix (MATRIX)31125.1 Description31125.2 Embedded Characteristics31125.2.1 Matrix Masters31225.2.2 Matrix Slaves31225.2.3 Master to Slave Access31325.3 Memory Mapping31325.4 Special Bus Granting Mechanism31325.4.1 No Default Master31425.4.2 Last Access Master31425.4.3 Fixed Default Master31425.5 Arbitration31425.5.1 Arbitration Scheduling31425.5.1.1 Undefined Length Burst Arbitration31525.5.1.2 Slot Cycle Limit Arbitration31525.5.2 Arbitration Priority Scheme31625.5.2.1 Fixed Priority Arbitration31625.5.2.2 Round-Robin Arbitration31625.6 Register Write Protection31725.7 Bus Matrix (MATRIX) User Interface31825.7.1 Bus Matrix Master Configuration Registers32025.7.2 Bus Matrix Slave Configuration Registers32125.7.3 Bus Matrix Priority Registers A For Slaves32225.7.4 Bus Matrix Priority Registers B For Slaves32325.7.5 Bus Matrix Master Remap Control Register32425.7.6 EBI Chip Select Assignment Register32525.7.7 Write Protection Mode Register32725.7.8 Write Protection Status Register32826. External Bus Interface (EBI)32926.1 Description32926.2 Embedded Characteristics32926.3 EBI Block Diagram33026.4 I/O Lines Description33126.5 Application Example33226.5.1 Hardware Interface33226.5.2 Product Dependencies33426.5.2.1 I/O Lines33426.5.3 Functional Description33426.5.3.1 Bus Multiplexing33426.5.3.2 Pull-up and Pull-down Control33426.5.3.3 Drive Level and Delay Control33526.5.3.4 Power supplies33626.5.3.5 Static Memory Controller33726.5.3.6 DDR2SDRAM Controller33726.5.3.7 Programmable Multibit ECC Controller33826.5.3.8 NAND Flash Support33826.5.4 Implementation Examples33926.5.4.1 2x8-bit DDR2 on EBI33926.5.4.2 16-bit LPDDR on EBI34026.5.4.3 16-bit SDRAM on EBI34126.5.4.4 2x16-bit SDRAM on EBI34226.5.4.5 8-bit NAND Flash with NFD0_ON_D16 = 034326.5.4.6 16-bit NAND Flash with NFD0_ON_D16 = 034426.5.4.7 8-bit NAND Flash with NFD0_ON_D16 = 134526.5.4.8 16-bit NAND Flash with NFD0_ON_D16 = 134626.5.4.9 NOR Flash on NCS034727. Programmable Multibit ECC Controller (PMECC)34827.1 Description34827.2 Embedded Characteristics34827.3 Block Diagram34927.4 Functional Description35027.4.1 MLC/SLC Write Page Operation using PMECC35227.4.1.1 SLC/MLC Write Operation with Spare Enable Bit Set35327.4.1.2 MLC/SLC Write Operation with Spare Area Disabled35327.4.2 MLC/SLC Read Page Operation using PMECC35427.4.2.1 MLC/SLC Read Operation with Spare Decoding35427.4.2.2 MLC/SLC Read Operation35427.4.2.3 MLC/SLC User Read ECC Area35527.5 Software Implementation35527.5.1 Remainder Substitution Procedure35527.5.2 Find the Error Location Polynomial Sigma(x)35627.5.3 Find the Error Position35927.6 Programmable Multibit ECC Controller (PMECC) User Interface36027.6.1 PMECC Configuration Register36227.6.2 PMECC Spare Area Size Register36427.6.3 PMECC Start Address Register36527.6.4 PMECC End Address Register36627.6.5 PMECC Clock Control Register36727.6.6 PMECC Control Register36827.6.7 PMECC Status Register36927.6.8 PMECC Interrupt Enable Register37027.6.9 PMECC Interrupt Disable Register37127.6.10 PMECC Interrupt Mask Register37227.6.11 PMECC Interrupt Status Register37327.6.12 PMECC ECC x Register37427.6.13 PMECC Remainder x Register37528. Programmable Multibit ECC Error Location Controller (PMERRLOC)37628.1 Description37628.2 Embedded Characteristics37628.3 Block Diagram37628.4 Functional Description37728.5 Programmable Multibit ECC Error Location Controller (PMERRLOC) User Interface37828.5.1 Error Location Configuration Register37928.5.2 Error Location Primitive Register38028.5.3 Error Location Enable Register38128.5.4 Error Location Disable Register38228.5.5 Error Location Status Register38328.5.6 Error Location Interrupt Enable Register38428.5.7 Error Location Interrupt Disable Register38528.5.8 Error Location Interrupt Mask Register38628.5.9 Error Location Interrupt Status Register38728.5.10 Error Location SIGMAx Register38828.5.11 PMECC Error Locationx Register38929. Static Memory Controller (SMC)39029.1 Description39029.2 Embedded Characteristics39029.3 I/O Lines Description39129.4 Multiplexed Signals39129.5 Application Example39229.5.1 Hardware Interface39229.6 Product Dependencies39229.6.1 I/O Lines39229.7 External Memory Mapping39329.8 Connection to External Devices39329.8.1 Data Bus Width39329.8.2 Byte Write or Byte Select Access39329.8.2.1 Byte Write Access39529.8.2.2 Byte Select Access39529.8.2.3 Signal Multiplexing39629.9 Standard Read and Write Protocols39729.9.1 Read Waveforms39729.9.1.1 NRD Waveform39729.9.1.2 NCS Waveform39729.9.1.3 Read Cycle39829.9.1.4 Null Delay Setup and Hold39829.9.1.5 Null Pulse39929.9.2 Read Mode39929.9.2.1 Read is Controlled by NRD (READ_MODE = 1):39929.9.2.2 Read is Controlled by NCS (READ_MODE = 0)39929.9.3 Write Waveforms40029.9.3.1 NWE Waveforms40029.9.3.2 NCS Waveforms40029.9.3.3 Write Cycle40129.9.3.4 Null Delay Setup and Hold40129.9.3.5 Null Pulse40229.9.4 Write Mode40229.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)40229.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)40329.9.5 Write Protected Registers40429.9.6 Coding Timing Parameters40429.9.7 Reset Values of Timing Parameters40429.9.8 Usage Restriction40429.10 Automatic Wait States40529.10.1 Chip Select Wait States40529.10.2 Early Read Wait State40629.10.3 Reload User Configuration Wait State40829.10.3.1 User Procedure40829.10.3.2 Slow Clock Mode Transition40829.10.4 Read to Write Wait State40829.11 Data Float Wait States40829.11.1 READ_MODE40929.11.2 TDF Optimization Enabled (TDF_MODE = 1)41129.11.3 TDF Optimization Disabled (TDF_MODE = 0)41129.12 External Wait41329.12.1 Restriction41329.12.2 Frozen Mode41429.12.3 Ready Mode41629.12.4 NWAIT Latency and Read/Write Timings41829.13 Slow Clock Mode41929.13.1 Slow Clock Mode Waveforms41929.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode42029.14 Asynchronous Page Mode42229.14.1 Protocol and Timings in Page Mode42229.14.2 Byte Access Type in Page Mode42329.14.3 Page Mode Restriction42329.14.4 Sequential and Non-sequential Accesses42329.15 Programmable IO Delays42529.16 Static Memory Controller (SMC) User Interface42629.16.1 SMC Setup Register42729.16.2 SMC Pulse Register42829.16.3 SMC Cycle Register42929.16.4 SMC MODE Register43029.16.5 SMC DELAY I/O Register43229.16.6 SMC Write Protect Mode Register43329.16.7 SMC Write Protect Status Register43430. DDR SDR SDRAM Controller (DDRSDRC)43530.1 Description43530.2 Embedded Characteristics43630.3 DDRSDRC Module Diagram43730.4 Initialization Sequence43830.4.1 SDR-SDRAM Initialization43830.4.2 Low-power DDR1-SDRAM Initialization43830.4.3 DDR2-SDRAM Initialization43930.5 Functional Description44130.5.1 SDRAM Controller Write Cycle44130.5.2 SDRAM Controller Read Cycle44630.5.3 Refresh (Auto-refresh Command)45030.5.4 Power Management45030.5.4.1 Self Refresh Mode45030.5.4.2 Power-down Mode45330.5.4.3 Deep Power-down Mode45430.5.4.4 Reset Mode45530.5.5 Multi-port Functionality45530.5.6 Write Protected Registers45830.6 Software Interface/SDRAM Organization, Address Mapping45930.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks45930.6.2 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Eight Banks46130.6.3 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width46130.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface46330.7.1 DDRSDRC Mode Register46430.7.2 DDRSDRC Refresh Timer Register46530.7.3 DDRSDRC Configuration Register46630.7.4 DDRSDRC Timing Parameter 0 Register46930.7.5 DDRSDRC Timing Parameter 1 Register47130.7.6 DDRSDRC Timing Parameter 2 Register47230.7.7 DDRSDRC Low-power Register47430.7.8 DDRSDRC Memory Device Register47630.7.9 DDRSDRC DLL Register47730.7.10 DDRSDRC High Speed Register47830.7.11 DDRSDRC Write Protect Mode Register47930.7.12 DDRSDRC Write Protect Status Register48031. DMA Controller (DMAC)48131.1 Description48131.2 Embedded Characteristics48131.2.1 DMA Controller 048231.2.2 DMA Controller 148331.3 Block Diagram48431.4 Functional Description48531.4.1 Basic Definitions48531.4.2 Memory Peripherals48831.4.3 Handshaking Interface48831.4.3.1 Software Handshaking48831.4.4 DMAC Transfer Types48931.4.4.1 Multi-buffer Transfers48931.4.4.2 Programming DMAC for Multiple Buffer Transfers49031.4.4.3 Ending Multi-buffer Transfers49231.4.5 Programming a Channel49231.4.5.1 Programming Examples49231.4.6 Disabling a Channel Prior to Transfer Completion51031.4.6.1 Abnormal Transfer Termination51031.5 DMAC Software Requirements51131.6 Write Protection Registers51231.7 DMA Controller (DMAC) User Interface51331.7.1 DMAC Global Configuration Register51431.7.2 DMAC Enable Register51531.7.3 DMAC Software Single Request Register51631.7.4 DMAC Software Chunk Transfer Request Register51731.7.5 DMAC Software Last Transfer Flag Register51831.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register51931.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register52031.7.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register52131.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register52231.7.10 DMAC Channel Handler Enable Register52331.7.11 DMAC Channel Handler Disable Register52431.7.12 DMAC Channel Handler Status Register52531.7.13 DMAC Channel x [x = 0..7] Source Address Register52631.7.14 DMAC Channel x [x = 0..7] Destination Address Register52731.7.15 DMAC Channel x [x = 0..7] Descriptor Address Register52831.7.16 DMAC Channel x [x = 0..7] Control A Register52931.7.17 DMAC Channel x [x = 0..7] Control B Register53131.7.18 DMAC Channel x [x = 0..7] Configuration Register53331.7.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register53531.7.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register53631.7.21 DMAC Write Protect Mode Register53731.7.22 DMAC Write Protect Status Register53832. USB High Speed Device Port (UDPHS)53932.1 Description53932.2 Embedded Characteristics53932.3 Block Diagram54032.4 Typical Connection54132.5 Product Dependencies54132.5.1 Power Management54132.5.2 Interrupt54132.6 Functional Description54232.6.1 UTMI Transceivers Sharing54232.6.2 USB V2.0 High Speed Device Port Introduction54232.6.3 USB V2.0 High Speed Transfer Types54232.6.4 USB Transfer Event Definitions54332.6.5 USB V2.0 High Speed BUS Transactions54332.6.6 Endpoint Configuration54432.6.7 DPRAM Management54632.6.8 Transfer With DMA54832.6.9 Transfer Without DMA54832.6.10 Handling Transactions with USB V2.0 Device Peripheral54932.6.10.1 Setup Transaction54932.6.10.2 NYET54932.6.10.3 Data IN55032.6.10.4 Bulk IN or Interrupt IN55032.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)55032.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)55132.6.10.7 Isochronous IN55432.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example55432.6.10.9 Data OUT55532.6.10.10 Bulk OUT or Interrupt OUT55532.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)55532.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device)55632.6.10.13 High Bandwidth Isochronous Endpoint OUT55732.6.10.14 Isochronous Endpoint Handling: OUT Example55832.6.10.15 STALL55832.6.11 Speed Identification55932.6.12 USB V2.0 High Speed Global Interrupt55932.6.13 Endpoint Interrupts55932.6.14 Power Modes56132.6.14.1 Controlling Device States56132.6.14.2 Not Powered State56232.6.14.3 Entering Attached State56232.6.14.4 From Powered State to Default State (Reset)56232.6.14.5 From Default State to Address State (Address Assigned)56232.6.14.6 From Address State to Configured State (Device Configured)56232.6.14.7 Entering Suspend State (Bus Activity)56232.6.14.8 Receiving a Host Resume56332.6.14.9 Sending an External Resume56332.6.15 Test Mode56332.7 USB High Speed Device Port (UDPHS) User Interface56432.7.1 UDPHS Control Register56532.7.2 UDPHS Frame Number Register56732.7.3 UDPHS Interrupt Enable Register56832.7.4 UDPHS Interrupt Status Register57032.7.5 UDPHS Clear Interrupt Register57232.7.6 UDPHS Endpoints Reset Register57332.7.7 UDPHS Test Register57432.7.8 UDPHS Endpoint Configuration Register57632.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)57832.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)58032.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints)58232.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint)58432.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)58632.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint)58932.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)59232.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)59332.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)59432.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)59632.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)59832.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint)60132.7.21 UDPHS DMA Channel Transfer Descriptor60532.7.22 UDPHS DMA Next Descriptor Address Register60632.7.23 UDPHS DMA Channel Address Register60732.7.24 UDPHS DMA Channel Control Register60832.7.25 UDPHS DMA Channel Status Register61033. USB Host High Speed Port (UHPHS)61233.1 Description61233.2 Embedded Characteristics61233.3 Block Diagram61333.4 Typical Connection61433.5 Product Dependencies61533.5.1 I/O Lines61533.5.2 Power Management61533.5.3 Interrupt61633.6 Functional Description61633.6.1 UTMI transceivers Sharing61633.6.2 EHCI61733.6.3 OHCI61734. High Speed MultiMedia Card Interface (HSMCI)61834.1 Description61834.2 Embedded Characteristics61834.3 Block Diagram61934.4 Application Block Diagram61934.5 Pin Name List62034.6 Product Dependencies62034.6.1 I/O Lines62034.6.2 Power Management62034.6.3 Interrupt62134.7 Bus Topology62134.8 High Speed MultiMedia Card Operations62334.8.1 Command - Response Operation62334.8.2 Data Transfer Operation62634.8.3 Read Operation62634.8.4 Write Operation62834.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller63034.8.6 READ_SINGLE_BLOCK Operation using DMA Controller63134.8.6.1 Block Length is Multiple of 463134.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)63234.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)63434.8.7 WRITE_MULTIPLE_BLOCK63534.8.7.1 One Block per Descriptor63534.8.8 READ_MULTIPLE_BLOCK63634.8.8.1 Block Length is a Multiple of 463634.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)63734.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1)63934.9 SD/SDIO Card Operation64034.9.1 SDIO Data Transfer Type64034.9.2 SDIO Interrupts64134.10 CE-ATA Operation64134.10.1 Executing an ATA Polling Command64134.10.2 Executing an ATA Interrupt Command64134.10.3 Aborting an ATA Command64134.10.4 CE-ATA Error Recovery64134.11 HSMCI Boot Operation Mode64234.11.1 Boot Procedure, Processor Mode64234.11.2 Boot Procedure DMA Mode64234.12 HSMCI Transfer Done Timings64334.12.1 Definition64334.12.2 Read Access64334.12.3 Write Access64334.13 Write Protection Registers64434.14 High Speed MultiMedia Card Interface (HSMCI) User Interface64534.14.1 HSMCI Control Register64634.14.2 HSMCI Mode Register64734.14.3 HSMCI Data Timeout Register64934.14.4 HSMCI SDCard/SDIO Register65034.14.5 HSMCI Argument Register65134.14.6 HSMCI Command Register65234.14.7 HSMCI Block Register65434.14.8 HSMCI Completion Signal Timeout Register65534.14.9 HSMCI Response Register65634.14.10 HSMCI Receive Data Register65734.14.11 HSMCI Transmit Data Register65834.14.12 HSMCI Status Register65934.14.13 HSMCI Interrupt Enable Register66234.14.14 HSMCI Interrupt Disable Register66434.14.15 HSMCI Interrupt Mask Register66634.14.16 HSMCI DMA Configuration Register66834.14.17 HSMCI Configuration Register66934.14.18 HSMCI Write Protect Mode Register67034.14.19 HSMCI Write Protect Status Register67134.14.20 HSMCI FIFOx Memory Aperture67235. Serial Peripheral Interface (SPI)67335.1 Description67335.2 Embedded Characteristics67335.3 Block Diagram67435.4 Application Block Diagram67435.5 Signal Description67535.6 Product Dependencies67535.6.1 I/O Lines67535.6.2 Power Management67535.6.3 Interrupt67635.6.4 Direct Memory Access Controller (DMAC)67635.7 Functional Description67635.7.1 Modes of Operation67635.7.2 Data Transfer67635.7.3 Master Mode Operations67835.7.3.1 Master Mode Block Diagram67935.7.3.2 Master Mode Flow Diagram68035.7.3.3 Clock Generation68135.7.3.4 Transfer Delays68135.7.3.5 Peripheral Selection68235.7.3.6 SPI Direct Access Memory Controller (DMAC)68235.7.3.7 Peripheral Chip Select Decoding68335.7.3.8 Peripheral Deselection without DMA68335.7.3.9 Peripheral Deselection with DMAC68435.7.3.10 Mode Fault Detection68535.7.4 SPI Slave Mode68535.7.5 Write Protected Registers68635.8 Serial Peripheral Interface (SPI) User Interface68735.8.1 SPI Control Register68835.8.2 SPI Mode Register68935.8.3 SPI Receive Data Register69135.8.4 SPI Transmit Data Register69235.8.5 SPI Status Register69335.8.6 SPI Interrupt Enable Register69435.8.7 SPI Interrupt Disable Register69535.8.8 SPI Interrupt Mask Register69635.8.9 SPI Chip Select Register69735.8.10 SPI Write Protection Mode Register70035.8.11 SPI Write Protection Status Register70136. Timer Counter (TC)70236.1 Description70236.2 Embedded Characteristics70236.3 Block Diagram70336.4 Pin Name List70436.5 Product Dependencies70436.5.1 I/O Lines70436.5.2 Power Management70436.5.3 Interrupt70436.6 Functional Description70536.6.1 TC Description70536.6.2 32-bit Counter70536.6.3 Clock Selection70536.6.4 Clock Control70736.6.5 TC Operating Modes70736.6.6 Trigger70836.6.7 Capture Operating Mode70836.6.8 Capture Registers A and B70836.6.9 Trigger Conditions70836.6.10 Waveform Operating Mode71036.6.11 Waveform Selection71036.6.11.1 WAVSEL = 0071236.6.11.2 WAVSEL = 1071336.6.11.3 WAVSEL = 0171436.6.11.4 WAVSEL = 1171536.6.12 External Event/Trigger Conditions71636.6.13 Output Controller71636.7 Timer Counter (TC) User Interface71736.7.1 TC Channel Control Register71836.7.2 TC Channel Mode Register: Capture Mode71936.7.3 TC Channel Mode Register: Waveform Mode72136.7.4 TC Counter Value Register72536.7.5 TC Register A72636.7.6 TC Register B72736.7.7 TC Register C72836.7.8 TC Status Register72936.7.9 TC Interrupt Enable Register73136.7.10 TC Interrupt Disable Register73236.7.11 TC Interrupt Mask Register73436.7.12 TC Block Control Register73536.7.13 TC Block Mode Register73637. Two-wire Interface (TWI)73737.1 Description73737.2 Embedded Characteristics73837.3 List of Abbreviations73837.4 Block Diagram73937.5 Application Block Diagram73937.5.1 I/O Lines Description73937.6 Product Dependencies74037.6.1 I/O Lines74037.6.2 Power Management74037.6.3 Interrupt74037.7 Functional Description74137.7.1 Transfer Format74137.7.2 Modes of Operation74137.8 Master Mode74237.8.1 Definition74237.8.2 Application Block Diagram74237.8.3 Programming Master Mode74237.8.4 Master Transmitter Mode74237.8.5 Master Receiver Mode74437.8.6 Internal Address74637.8.6.1 7-bit Slave Addressing74637.8.6.2 10-bit Slave Addressing74737.8.7 Using the DMA Controller74737.8.7.1 Data Transmit with the DMA74737.8.7.2 Data Receive with the DMA74737.8.8 SMBUS Quick Command (Master Mode Only)74837.8.9 Read-write Flowcharts74837.9 Multi-master Mode75537.9.1 Definition75537.9.2 Different Multi-master Modes75537.9.2.1 TWI as Master Only75537.9.2.2 TWI as Master or Slave75537.10 Slave Mode75837.10.1 Definition75837.10.2 Application Block Diagram75837.10.3 Programming Slave Mode75837.10.4 Receiving Data75837.10.4.1 Read Sequence75837.10.4.2 Write Sequence75937.10.4.3 Clock Synchronization Sequence75937.10.4.4 General Call75937.10.5 Data Transfer75937.10.5.1 Read Operation75937.10.5.2 Write Operation76037.10.5.3 General Call76037.10.5.4 Clock Synchronization76137.10.5.5 Reversal after a Repeated Start76337.10.6 Read Write Flowcharts76437.11 Write Protection System76537.12 Two-wire Interface (TWI) User Interface76637.12.1 TWI Control Register76737.12.2 TWI Master Mode Register76937.12.3 TWI Slave Mode Register77037.12.4 TWI Internal Address Register77137.12.5 TWI Clock Waveform Generator Register77237.12.6 TWI Status Register77337.12.7 TWI Interrupt Enable Register77637.12.8 TWI Interrupt Disable Register77737.12.9 TWI Interrupt Mask Register77837.12.10 TWI Receive Holding Register77937.12.11 TWI Transmit Holding Register78037.12.12 TWI Write Protection Mode Register78137.12.13 TWI Write Protection Status Register78238. Pulse Width Modulation Controller (PWM)78338.1 Description78338.2 Embedded characteristics78338.3 Block Diagram78438.4 I/O Lines Description78538.5 Product Dependencies78538.5.1 I/O Lines78538.5.2 Power Management78538.5.3 Interrupt Sources78538.6 Functional Description78638.6.1 PWM Clock Generator78638.6.2 PWM Channel78738.6.2.1 Block Diagram78738.6.2.2 Waveform Properties78738.6.3 PWM Controller Operations79038.6.3.1 Initialization79038.6.3.2 Source Clock Selection Criteria79038.6.3.3 Changing the Duty Cycle or the Period79038.6.3.4 Interrupts79238.7 Pulse Width Modulation Controller (PWM) User Interface79338.7.1 PWM Mode Register79438.7.2 PWM Enable Register79538.7.3 PWM Disable Register79638.7.4 PWM Status Register79738.7.5 PWM Interrupt Enable Register79838.7.6 PWM Interrupt Disable Register79938.7.7 PWM Interrupt Mask Register80038.7.8 PWM Interrupt Status Register80138.7.9 PWM Channel Mode Register80238.7.10 PWM Channel Duty Cycle Register80438.7.11 PWM Channel Period Register80538.7.12 PWM Channel Counter Register80638.7.13 PWM Channel Update Register80739. Universal Synchronous Asynchronous Receiver Transmitter (USART)80839.1 Description80839.2 Embedded Characteristics80939.3 Block Diagram81039.4 Application Block Diagram81139.5 I/O Lines Description81239.6 Product Dependencies81339.6.1 I/O Lines81339.6.2 Power Management81339.6.3 Interrupt81439.7 Functional Description81539.7.1 Baud Rate Generator81639.7.1.1 Baud Rate in Asynchronous Mode81639.7.1.2 Fractional Baud Rate in Asynchronous Mode81839.7.1.3 Baud Rate in Synchronous Mode or SPI Mode81839.7.1.4 Baud Rate in ISO 7816 Mode81939.7.2 Receiver and Transmitter Control82039.7.3 Synchronous and Asynchronous Modes82039.7.3.1 Transmitter Operations82039.7.3.2 Manchester Encoder82139.7.3.3 Asynchronous Receiver82339.7.3.4 Manchester Decoder82439.7.3.5 Radio Interface: Manchester Encoded USART Application82639.7.3.6 Synchronous Receiver82739.7.3.7 Receiver Operations82839.7.3.8 Parity82839.7.3.9 Multidrop Mode82939.7.3.10 Transmitter Timeguard82939.7.3.11 Receiver Time-out83039.7.3.12 Framing Error83239.7.3.13 Transmit Break83239.7.3.14 Receive Break83339.7.3.15 Hardware Handshaking83439.7.4 ISO7816 Mode83439.7.4.1 ISO7816 Mode Overview83439.7.4.2 Protocol T = 083539.7.4.3 Protocol T = 183639.7.5 IrDA Mode83639.7.5.1 IrDA Modulation83739.7.5.2 IrDA Baud Rate83839.7.5.3 IrDA Demodulator83839.7.6 RS485 Mode83939.7.7 SPI Mode84039.7.7.1 Modes of Operation84039.7.7.2 Baud Rate84139.7.7.3 Data Transfer84239.7.7.4 Receiver and Transmitter Control84339.7.7.5 Character Transmission84339.7.7.6 Character Reception84439.7.7.7 Receiver Timeout84439.7.8 LIN Mode84439.7.8.1 Modes of Operation84439.7.8.2 Baud Rate Configuration84439.7.8.3 Receiver and Transmitter Control84439.7.8.4 Character Transmission84439.7.8.5 Character Reception84439.7.8.6 Header Transmission (Master Node Configuration)84539.7.8.7 Header Reception (Slave Node Configuration)84539.7.8.8 Slave Node Synchronization84639.7.8.9 Identifier Parity84839.7.8.10 Node Action84839.7.8.11 Response Data Length84939.7.8.12 Checksum84939.7.8.13 Frame Slot Mode85039.7.8.14 LIN Errors85039.7.8.15 LIN Frame Handling85139.7.8.16 LIN Frame Handling With The DMAC85439.7.8.17 Wake-up Request85639.7.8.18 Bus Idle Time-out85639.7.9 Test Modes85739.7.9.1 Normal Mode85739.7.9.2 Automatic Echo Mode85739.7.9.3 Local Loopback Mode85739.7.9.4 Remote Loopback Mode85839.7.10 Write Protection Registers85939.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface86039.8.1 USART Control Register86139.8.2 USART Control Register (SPI_MODE)86339.8.3 USART Mode Register86539.8.4 USART Mode Register (SPI_MODE)86839.8.5 USART Interrupt Enable Register87039.8.6 USART Interrupt Enable Register (SPI_MODE)87139.8.7 USART Interrupt Enable Register (LIN_MODE)87239.8.8 USART Interrupt Disable Register87339.8.9 USART Interrupt Disable Register (SPI_MODE)87439.8.10 USART Interrupt Disable Register (LIN_MODE)87539.8.11 USART Interrupt Mask Register87639.8.12 USART Interrupt Mask Register (SPI_MODE)87739.8.13 USART Interrupt Mask Register (LIN_MODE)87839.8.14 USART Channel Status Register87939.8.15 USART Channel Status Register (SPI_MODE)88139.8.16 USART Channel Status Register (LIN_MODE)88239.8.17 USART Receive Holding Register88439.8.18 USART Transmit Holding Register88539.8.19 USART Baud Rate Generator Register88639.8.20 USART Receiver Time-out Register88739.8.21 USART Transmitter Timeguard Register88839.8.22 USART FI DI RATIO Register88939.8.23 USART Number of Errors Register89039.8.24 USART IrDA FILTER Register89139.8.25 USART Manchester Configuration Register89239.8.26 USART LIN Mode Register89439.8.27 USART LIN Identifier Register89639.8.28 USART LIN Baud Rate Register89739.8.29 USART Write Protect Mode Register89839.8.30 USART Write Protect Status Register89940. Analog-to-Digital Converter (ADC)90040.1 Description90040.2 Embedded Characteristics90040.3 Block Diagram90140.4 Signal Description90140.5 Product Dependencies90240.5.1 Power Management90240.5.2 Interrupt Sources90240.5.3 Analog Inputs90240.5.4 I/O Lines90240.5.5 Timer Triggers90240.5.6 Conversion Performances90240.6 Functional Description90340.6.1 Analog-to-digital Conversion90340.6.2 Conversion Reference90340.6.3 Conversion Resolution90340.6.4 Conversion Results90440.6.5 Conversion Triggers90540.6.6 Sleep Mode and Conversion Sequencer90640.6.7 Comparison Window90740.6.8 ADC Timings90740.6.9 Buffer Structure90740.6.10 Write Protected Registers90740.7 Analog-to-Digital Converter (ADC) User Interface90840.7.1 ADC Control Register90940.7.2 ADC Mode Register91040.7.3 ADC Channel Sequence 1 Register91240.7.4 ADC Channel Sequence 2 Register91340.7.5 ADC Channel Enable Register91440.7.6 ADC Channel Disable Register91540.7.7 ADC Channel Status Register91640.7.8 ADC Last Converted Data Register91740.7.9 ADC Interrupt Enable Register91840.7.10 ADC Interrupt Disable Register91940.7.11 ADC Interrupt Mask Register92040.7.12 ADC Interrupt Status Register92140.7.13 ADC Overrun Status Register92240.7.14 ADC Extended Mode Register92340.7.15 ADC Compare Window Register92440.7.16 ADC Channel Data Register92540.7.17 ADC Trigger Register92640.7.18 ADC Write Protect Mode Register92740.7.19 ADC Write Protect Status Register92841. Universal Asynchronous Receiver Transmitter (UART)92941.1 Description92941.2 Embedded Characteristics92941.3 Block Diagram93041.4 Product Dependencies93141.4.1 I/O Lines93141.4.2 Power Management93141.4.3 Interrupt Source93141.5 UART Operations93141.5.1 Baud Rate Generator93141.5.2 Receiver93241.5.2.1 Receiver Reset, Enable and Disable93241.5.2.2 Start Detection and Data Sampling93241.5.2.3 Receiver Ready93341.5.2.4 Receiver Overrun93341.5.2.5 Parity Error93341.5.2.6 Receiver Framing Error93441.5.3 Transmitter93441.5.3.1 Transmitter Reset, Enable and Disable93441.5.3.2 Transmit Format93441.5.3.3 Transmitter Control93541.5.4 DMA Support93541.5.5 Test Modes93541.6 Universal Asynchronous Receiver Transmitter (UART) User Interface93741.6.1 UART Control Register93841.6.2 UART Mode Register93941.6.3 UART Interrupt Enable Register94041.6.4 UART Interrupt Disable Register94141.6.5 UART Interrupt Mask Register94241.6.6 UART Status Register94341.6.7 UART Receiver Holding Register94441.6.8 UART Transmit Holding Register94541.6.9 UART Baud Rate Generator Register94642. Software Modem Device (SMD)94742.1 Description94742.2 Embedded Characteristics94842.3 Block Diagram94843. Synchronous Serial Controller (SSC)94943.1 Description94943.2 Embedded Characteristics94943.3 Block Diagram95043.4 Application Block Diagram95043.5 Pin Name List95143.6 Product Dependencies95143.6.1 I/O Lines95143.6.2 Power Management95143.6.3 Interrupt95143.7 Functional Description95243.7.1 Clock Management95343.7.1.1 Clock Divider95343.7.1.2 Transmitter Clock Management95443.7.1.3 Receiver Clock Management95443.7.1.4 Serial Clock Ratio Considerations95543.7.2 Transmitter Operations95543.7.3 Receiver Operations95643.7.4 Start95743.7.5 Frame Sync95943.7.5.1 Frame Sync Data95943.7.5.2 Frame Sync Edge Detection95943.7.6 Receive Compare Modes95943.7.6.1 Compare Functions95943.7.7 Data Format96043.7.8 Loop Mode96143.7.9 Interrupt96143.8 SSC Application Examples96343.8.1 Write Protection Registers96543.9 Synchronous Serial Controller (SSC) User Interface96643.9.1 SSC Control Register96743.9.2 SSC Clock Mode Register96843.9.3 SSC Receive Clock Mode Register96943.9.4 SSC Receive Frame Mode Register97143.9.5 SSC Transmit Clock Mode Register97343.9.6 SSC Transmit Frame Mode Register97543.9.7 SSC Receive Holding Register97743.9.8 SSC Transmit Holding Register97843.9.9 SSC Receive Synchronization Holding Register97943.9.10 SSC Transmit Synchronization Holding Register98043.9.11 SSC Receive Compare 0 Register98143.9.12 SSC Receive Compare 1 Register98243.9.13 SSC Status Register98343.9.14 SSC Interrupt Enable Register98543.9.15 SSC Interrupt Disable Register98743.9.16 SSC Interrupt Mask Register98943.9.17 SSC Write Protect Mode Register99143.9.18 SSC Write Protect Status Register99244. Image Sensor Interface (ISI)99344.1 Description99344.2 Embedded Characteristics99444.3 Block Diagram99444.4 Functional Description99544.4.1 Data Timing99544.4.2 Data Ordering99644.4.3 Clocks99744.4.4 Preview Path99844.4.4.1 Scaling, Decimation (Subsampling)99844.4.4.2 Color Space Conversion99944.4.4.3 Memory Interface100044.4.4.4 FIFO and DMA Features100044.4.5 Codec Path100144.4.5.1 Color Space Conversion100144.4.5.2 Memory Interface100144.4.5.3 DMA Features100144.5 Image Sensor Interface (ISI) User Interface100244.5.1 ISI Configuration 1 Register100344.5.2 ISI Configuration 2 Register100544.5.3 ISI Preview Register100744.5.4 ISI Preview Decimation Factor Register100844.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register100944.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register101044.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register101144.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register101244.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register101344.5.10 ISI Control Register101444.5.11 ISI Status Register101544.5.12 ISI Interrupt Enable Register101744.5.13 ISI Interrupt Disable Register101844.5.14 ISI Interrupt Mask Register101944.5.15 DMA Channel Enable Register102144.5.16 DMA Channel Disable Register102244.5.17 DMA Channel Status Register102344.5.18 DMA Preview Base Address Register102444.5.19 DMA Preview Control Register102544.5.20 DMA Preview Descriptor Address Register102644.5.21 DMA Codec Base Address Register102744.5.22 DMA Codec Control Register102844.5.23 DMA Codec Descriptor Address Register102944.5.24 ISI Write Protection Control103044.5.25 ISI Write Protection Status103145. Ethernet MAC 10/100 (EMAC)103245.1 Description103245.2 Embedded Characteristics103245.3 Block Diagram103345.4 Functional Description103445.4.1 Clock103445.4.2 Memory Interface103445.4.2.1 FIFO103445.4.2.2 Receive Buffers103545.4.2.3 Transmit Buffer103745.4.3 Transmit Block103845.4.4 Pause Frame Support103945.4.5 Receive Block103945.4.6 Address Checking Block103945.4.7 Broadcast Address104045.4.8 Hash Addressing104145.4.9 Copy All Frames (or Promiscuous Mode)104145.4.10 Type ID Checking104145.4.11 VLAN Support104145.4.12 PHY Maintenance104245.4.13 Physical Interface104245.4.13.1 RMII Transmit and Receive Operation104345.5 Programming Interface104345.5.1 Initialization104345.5.1.1 Configuration104345.5.1.2 Receive Buffer List104345.5.1.3 Transmit Buffer List104445.5.1.4 Address Matching104445.5.1.5 Interrupts104445.5.1.6 Transmitting Frames104445.5.1.7 Receiving Frames104545.6 Ethernet MAC 10/100 (EMAC) User Interface104645.6.1 Network Control Register104845.6.2 Network Configuration Register105045.6.3 Network Status Register105245.6.4 Transmit Status Register105345.6.5 Receive Buffer Queue Pointer Register105445.6.6 Transmit Buffer Queue Pointer Register105545.6.7 Receive Status Register105645.6.8 Interrupt Status Register105745.6.9 Interrupt Enable Register105945.6.10 Interrupt Disable Register106145.6.11 Interrupt Mask Register106345.6.12 PHY Maintenance Register106545.6.13 Pause Time Register106645.6.14 Hash Register Bottom106745.6.15 Hash Register Top106845.6.16 Specific Address 1 Bottom Register106945.6.17 Specific Address 1 Top Register107045.6.18 Specific Address 2 Bottom Register107145.6.19 Specific Address 2 Top Register107245.6.20 Specific Address 3 Bottom Register107345.6.21 Specific Address 3 Top Register107445.6.22 Specific Address 4 Bottom Register107545.6.23 Specific Address 4 Top Register107645.6.24 Type ID Checking Register107745.6.25 User Input/Output Register107845.6.26 EMAC Statistic Registers107945.6.26.1 Pause Frames Received Register108045.6.26.2 Frames Transmitted OK Register108145.6.26.3 Single Collision Frames Register108245.6.26.4 Multicollision Frames Register108345.6.26.5 Frames Received OK Register108445.6.26.6 Frames Check Sequence Errors Register108545.6.26.7 Alignment Errors Register108645.6.26.8 Deferred Transmission Frames Register108745.6.26.9 Late Collisions Register108845.6.26.10 Excessive Collisions Register108945.6.26.11 Transmit Underrun Errors Register109045.6.26.12 Carrier Sense Errors Register109145.6.26.13 Receive Resource Errors Register109245.6.26.14 Receive Overrun Errors Register109345.6.26.15 Receive Symbol Errors Register109445.6.26.16 Excessive Length Errors Register109545.6.26.17 Receive Jabbers Register109645.6.26.18 Undersize Frames Register109745.6.26.19 SQE Test Errors Register109845.6.26.20 Received Length Field Mismatch Register109946. Electrical Characteristics110046.1 Absolute Maximum Ratings110046.2 DC Characteristics110146.3 Power Consumption110246.3.1 Power Consumption versus Modes110246.4 Clock Characteristics110446.4.1 Processor Clock Characteristics110446.4.2 Master Clock Characteristics110446.5 Main Oscillator Characteristics110446.5.1 Crystal Oscillator Characteristics110546.5.2 XIN Clock Characteristics110546.6 12 MHz RC Oscillator Characteristics110646.7 32 kHz Oscillator Characteristics110646.7.1 32 kHz Crystal Characteristics110746.7.2 XIN32 Clock Characteristics110746.8 32 kHz RC Oscillator Characteristics110746.9 PLL Characteristics110846.9.1 UTMI PLL Characteristics110846.10 I/Os110946.11 USB HS Characteristics110946.12 USB Transceiver Characteristics111046.13 Analog-to-Digital Converter (ADC)111146.14 POR Characteristics111246.14.1 Core Power Supply POR Characteristics111246.14.2 Backup Power Supply POR Characteristics111246.15 Power Sequence Requirements111246.15.1 Power-Up Sequence111346.16 SMC Timings111446.16.1 Timing Conditions111446.16.2 Timing Extraction111446.16.2.1 Zero Hold Mode Restrictions111446.16.2.2 Read Timings111546.16.2.3 Write Timings111646.17 DDRSDRC Timings111746.18 Peripheral Timings111846.18.1 SPI111846.18.1.1 Maximum SPI Frequency111846.18.1.2 Timing Conditions111846.18.1.3 Timing Extraction111846.18.2 SSC112246.18.2.1 Timing conditions112246.18.2.2 Timing Extraction112246.18.3 ISI112646.18.3.1 Timing conditions112646.18.3.2 Timing Extraction112646.18.4 HSMCI112746.18.5 EMAC112746.18.5.1 Timing conditions112746.18.5.2 Timing constraints112746.18.5.3 MII Mode112746.18.5.4 RMII Mode112946.18.6 USART in SPI Mode Timings113046.18.6.1 Timing conditions113046.18.6.2 Timing extraction113046.19 Two-wire Interface Characteristics113347. Mechanical Overview113547.1 217-ball BGA Package113547.2 247-ball BGA Packages113747.2.1 247-ball TFBGA package113747.2.2 247-ball VFBGA package113947.3 Marking114048. SAM9G25 Ordering Information114149. SAM9G25 Errata114249.1 External Bus Interface (EBI)114249.1.1 EBI: Data lines are Hi-Z after reset114249.2 Reset Controller (RSTC)114249.2.1 RSTC: Reset during SDRAM Accesses114249.3 Static Memory Controller (SMC)114249.3.1 SMC: SMC DELAY I/O Registers are write-only114249.4 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)114249.4.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL114249.5 Timer Counter (TC)114349.5.1 TC: The TIOA5 signal is not well connected114349.6 Boot Strategy114349.6.1 NAND Flash Boot Detection using ONFI parameters does not work114349.7 Real Time Clock (RTC)114449.7.1 RTC: Interrupt Mask Register cannot be used1144Revision History1145Table of Contents1157サイズ： 5.03MBページ数： 1165Language: Englishマニュアルを開く
