データシート (ATSAM4E-XPRO)目次Preface1Table of Contents21. Introduction31.1. Features31.2. Kit Overview32. Getting Started52.1. Quick-start52.2. Connecting the Kit52.3. Design Documentation and Related Links53. Xplained Pro63.1. Embedded Debugger63.2. Hardware Identification System63.3. Power Supply73.3.1. Measuring SAM4E Power Consumption73.4. Standard Headers and Connectors73.4.1. Xplained Pro Standard Extension Header73.4.2. Xplained Pro LCD Connector83.4.3. Xplained Pro Power Header104. Hardware User Guide114.1. Connectors114.1.1. I/O Extension Headers114.1.2. LCD Extension Connector124.1.3. Chip Erase Header144.1.4. Other Headers144.2. Peripherals144.2.1. SRAM144.2.2. NAND Flash154.2.3. Ethernet164.2.4. SD Card Connector174.2.5. CAN174.2.6. USB174.2.7. Crystals174.2.8. Mechanical Buttons184.2.9. LED184.3. Embedded Debugger Implementation184.3.1. Serial Wire Debug184.3.2. Virtual COM Port184.3.3. Atmel Data Gateway Interface195. Kit Specific Data206. Hardware Revision History and Known Issues216.1. Identifying Product ID and Revision216.2. Revision 3217. Document Revision History228. Evaluation Board/Kit Important Notice23サイズ： 820KBページ数： 24Language: Englishマニュアルを開く
データシート (ATSAM4E-XPRO)目次Description11. Features21.1 Configuration Summary42. Block Diagram53. Signal Description74. Package and Pinout114.1 100-ball TFBGA Package and Pinout114.1.1 100-ball TFBGA Package Outline114.1.2 100-ball TFBGA Pinout114.2 144-ball LFBGA Package and Pinout124.2.1 144-ball LFBGA Package Outline124.2.2 144-ball LFBGA Pinout124.3 100-lead LQFP Package and Pinout134.3.1 100-lead LQFP Package Outline134.3.2 100-lead LQFP Pinout134.4 144-lead LQFP Package and Pinout144.4.1 144-lead LQFP Package Outline144.4.2 144-lead LQFP Pinout145. Power Considerations155.1 Power Supplies155.2 Voltage Regulator155.3 Typical Powering Schematics155.5 Low-power Modes165.5.1 Backup Mode165.5.2 Wait Mode175.5.3 Sleep Mode185.5.4 Low-power Mode Summary Table195.6 Wake-up Sources205.7 Fast Start-up216. Input/Output Lines226.1 General Purpose I/O Lines226.2 System I/O Lines237. Product Mapping248. Memories258.1 Embedded Memories258.1.1 Internal SRAM258.1.2 Internal ROM258.1.3 Embedded Flash258.1.3.1 Flash Overview258.1.3.2 Enhanced Embedded Flash Controller278.1.3.3 Flash Speed278.1.3.4 Lock Regions278.1.3.5 Security Bit Feature278.1.3.6 Calibration Bits288.1.3.7 Unique Identifier288.1.3.8 User Signature288.1.3.9 Fast Flash Programming Interface288.1.3.10 SAM-BA Boot288.1.3.11 GPNVM Bits288.1.4 Boot Strategies298.2 External Memories308.3 Cortex-M Cache Controller (CMCC)309. Real-time Event Management319.1 Embedded Characteristics319.2 Real-time Event Mapping List3210. System Controller3310.1 System Controller and Peripherals Mapping3410.2 Power-on-Reset, Brownout and Supply Monitor3510.2.1 Power-on-Reset3510.2.2 Brownout Detector on VDDCORE3510.2.3 Supply Monitor on VDDIO3510.3 Reset Controller3511. Peripherals3711.1 Peripheral Identifiers3711.2 Peripheral Signal Multiplexing on I/O Lines3911.2.1 PIO Controller A Multiplexing4011.2.2 PIO Controller B Multiplexing4111.2.3 PIO Controller C Multiplexing4211.2.4 PIO Controller D Multiplexing4311.2.5 PIO Controller E Multiplexing4412. ARM Cortex-M4 Processor4512.1 Description4512.1.1 System Level Interface4512.1.2 Integrated Configurable Debug4512.2 Embedded Characteristics4612.3 Block Diagram4612.4 Cortex-M4 Models4712.4.1 Programmers Model4712.4.1.1 Processor Modes and Privilege Levels for Software Execution4712.4.1.2 Stacks4712.4.1.3 Core Registers4812.4.1.4 General-purpose Registers4912.4.1.5 Stack Pointer4912.4.1.6 Link Register4912.4.1.7 Program Counter4912.4.1.8 Program Status Register5012.4.1.9 Application Program Status Register5112.4.1.10 Interrupt Program Status Register5212.4.1.11 Execution Program Status Register5312.4.1.12 Exception Mask Registers5412.4.1.13 Priority Mask Register5512.4.1.14 Fault Mask Register5612.4.1.15 Base Priority Mask Register5712.4.1.16 Control Register5812.4.1.17 Exceptions and Interrupts6012.4.1.18 Data Types6012.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)6012.4.2 Memory Model6112.4.2.1 Memory Regions, Types and Attributes6112.4.2.2 Memory System Ordering of Memory Accesses6212.4.2.3 Behavior of Memory Accesses6312.4.2.4 Software Ordering of Memory Accesses6412.4.2.5 Bit-banding6412.4.2.6 Memory Endianness6612.4.2.7 Synchronization Primitives6712.4.2.8 Programming Hints for the Synchronization Primitives6812.4.3 Exception Model6812.4.3.1 Exception States6812.4.3.2 Exception Types6912.4.3.3 Exception Handlers7112.4.3.4 Vector Table7112.4.3.5 Exception Priorities7212.4.3.6 Interrupt Priority Grouping7212.4.3.7 Exception Entry and Return7212.4.3.8 Fault Handling7612.5 Power Management7812.5.1 Entering Sleep Mode7812.5.1.1 Wait for Interrupt7812.5.1.2 Wait for Event7812.5.1.3 Sleep-on-exit7812.5.2 Wakeup from Sleep Mode7812.5.2.1 Wakeup from WFI or Sleep-on-exit7812.5.2.2 Wakeup from WFE7812.5.2.3 External Event Input7912.5.3 Power Management Programming Hints7912.6 Cortex-M4 Instruction Set8012.6.1 Instruction Set Summary8012.6.2 CMSIS Functions8612.6.3 Instruction Descriptions8712.6.3.1 Operands8712.6.3.2 Restrictions when Using PC or SP8712.6.3.3 Flexible Second Operand8712.6.3.4 Shift Operations8812.6.3.5 Address Alignment9012.6.3.6 PC-relative Expressions9012.6.3.7 Conditional Execution9112.6.3.8 Instruction Width Selection9312.6.4 Memory Access Instructions9412.6.4.1 ADR9512.6.4.2 LDR and STR, Immediate Offset9612.6.4.3 LDR and STR, Register Offset9812.6.4.4 LDR and STR, Unprivileged10012.6.4.5 LDR, PC-relative10112.6.4.6 LDM and STM10212.6.4.7 PUSH and POP10412.6.4.8 LDREX and STREX10512.6.4.9 CLREX10612.6.5 General Data Processing Instructions10712.6.5.1 ADD, ADC, SUB, SBC, and RSB10912.6.5.2 AND, ORR, EOR, BIC, and ORN11112.6.5.3 ASR, LSL, LSR, ROR, and RRX11312.6.5.4 CLZ11412.6.5.5 CMP and CMN11512.6.5.6 MOV and MVN11612.6.5.7 MOVT11712.6.5.8 REV, REV16, REVSH, and RBIT11812.6.5.9 SADD16 and SADD811912.6.5.10 SHADD16 and SHADD812012.6.5.11 SHASX and SHSAX12112.6.5.12 SHSUB16 and SHSUB812212.6.5.13 SSUB16 and SSUB812312.6.5.14 SASX and SSAX12412.6.5.15 TST and TEQ12512.6.5.16 UADD16 and UADD812612.6.5.17 UASX and USAX12712.6.5.18 UHADD16 and UHADD812812.6.5.19 UHASX and UHSAX12912.6.5.20 UHSUB16 and UHSUB813012.6.5.21 SEL13112.6.5.22 USAD813212.6.5.23 USADA813312.6.5.24 USUB16 and USUB813412.6.6 Multiply and Divide Instructions13512.6.6.1 MUL, MLA, and MLS13612.6.6.2 UMULL, UMAAL, UMLAL13712.6.6.3 SMLA and SMLAW13812.6.6.4 SMLAD14012.6.6.5 SMLAL and SMLALD14112.6.6.6 SMLSD and SMLSLD14312.6.6.7 SMMLA and SMMLS14512.6.6.8 SMMUL14712.6.6.9 SMUAD and SMUSD14812.6.6.10 SMUL and SMULW15012.6.6.11 UMULL, UMLAL, SMULL, and SMLAL15212.6.6.12 SDIV and UDIV15312.6.7 Saturating Instructions15412.6.7.1 SSAT and USAT15512.6.7.2 SSAT16 and USAT1615612.6.7.3 QADD and QSUB15712.6.7.4 QASX and QSAX15912.6.7.5 QDADD and QDSUB16012.6.7.6 UQASX and UQSAX16112.6.7.7 UQADD and UQSUB16312.6.8 Packing and Unpacking Instructions16412.6.8.1 PKHBT and PKHTB16512.6.8.2 SXT and UXT16612.6.8.3 SXTA and UXTA16712.6.9 Bitfield Instructions16812.6.9.1 BFC and BFI16912.6.9.2 SBFX and UBFX17012.6.9.3 SXT and UXT17112.6.10 Branch and Control Instructions17212.6.10.1 B, BL, BX, and BLX17312.6.10.2 CBZ and CBNZ17512.6.10.3 IT17612.6.10.4 TBB and TBH17812.6.11 Floating-point Instructions18012.6.11.1 VABS18212.6.11.2 VADD18312.6.11.3 VCMP, VCMPE18412.6.11.4 VCVT, VCVTR between Floating-point and Integer18512.6.11.5 VCVT between Floating-point and Fixed-point18612.6.11.6 VCVTB, VCVTT18712.6.11.7 VDIV18812.6.11.8 VFMA, VFMS18912.6.11.9 VFNMA, VFNMS19012.6.11.10 VLDM19112.6.11.11 VLDR19212.6.11.12 VLMA, VLMS19312.6.11.13 VMOV Immediate19412.6.11.14 VMOV Register19512.6.11.15 VMOV Scalar to ARM Core Register19612.6.11.16 VMOV ARM Core Register to Single Precision19712.6.11.17 VMOV Two ARM Core Registers to Two Single Precision19812.6.11.18 VMOV ARM Core Register to Scalar19912.6.11.19 VMRS20012.6.11.20 VMSR20112.6.11.21 VMUL20212.6.11.22 VNEG20312.6.11.23 VNMLA, VNMLS, VNMUL20412.6.11.24 VPOP20512.6.11.25 VPUSH20612.6.11.26 VSQRT20712.6.11.27 VSTM20812.6.11.28 VSTR20912.6.11.29 VSUB21012.6.12 Miscellaneous Instructions21112.6.12.1 BKPT21212.6.12.2 CPS21212.6.12.3 DMB21312.6.12.4 DSB21412.6.12.5 ISB21412.6.12.6 MRS21512.6.12.7 MSR21512.6.12.8 NOP21612.6.12.9 SEV21712.6.12.10 SVC21712.6.12.11 WFE21812.6.12.12 WFI21812.7 Cortex-M4 Core Peripherals21912.7.1 Peripherals21912.7.2 Address Map21912.8 Nested Vectored Interrupt Controller (NVIC)22012.8.1 Level-sensitive Interrupts22012.8.1.1 Hardware and Software Control of Interrupts22012.8.2 NVIC Design Hints and Tips22012.8.2.1 NVIC Programming Hints22112.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface22312.8.3.1 Interrupt Set-enable Registers22412.8.3.2 Interrupt Clear-enable Registers22512.8.3.3 Interrupt Set-pending Registers22612.8.3.4 Interrupt Clear-pending Registers22712.8.3.5 Interrupt Active Bit Registers22812.8.3.6 Interrupt Priority Registers22912.8.3.7 Software Trigger Interrupt Register23012.9 System Control Block (SCB)23112.9.1 System Control Block (SCB) User Interface23212.9.1.1 Auxiliary Control Register23312.9.1.2 CPUID Base Register23412.9.1.3 Interrupt Control and State Register23512.9.1.4 Vector Table Offset Register23712.9.1.5 Application Interrupt and Reset Control Register23812.9.1.6 System Control Register24012.9.1.7 Configuration and Control Register24112.9.1.8 System Handler Priority Registers24312.9.1.9 System Handler Priority Register 124412.9.1.10 System Handler Priority Register 224512.9.1.11 System Handler Priority Register 324612.9.1.12 System Handler Control and State Register24712.9.1.13 Configurable Fault Status Register25012.9.1.14 Configurable Fault Status Register (Byte Access)25412.9.1.15 Hard Fault Status Register25512.9.1.16 MemManage Fault Address Register25612.9.1.17 Bus Fault Address Register25712.10 System Timer (SysTick)25812.10.1 System Timer (SysTick) User Interface25912.10.1.1 SysTick Control and Status26012.10.1.2 SysTick Reload Value Registers26112.10.1.3 SysTick Current Value Register26212.10.1.4 SysTick Calibration Value Register26312.11 Memory Protection Unit (MPU)26412.11.1 MPU Access Permission Attributes26412.11.1.1 MPU Mismatch26612.11.1.2 Updating an MPU Region26612.11.1.3 Updating an MPU Region Using Separate Words26612.11.1.4 Updating an MPU Region Using Multi-word Writes26712.11.1.5 Subregions26812.11.1.6 Example of SRD Use26812.11.1.7 MPU Design Hints And Tips26812.11.2 Memory Protection Unit (MPU) User Interface27012.11.2.1 MPU Type Register27112.11.2.2 MPU Control Register27212.11.2.3 MPU Region Number Register27412.11.2.4 MPU Region Base Address Register27512.11.2.5 MPU Region Attribute and Size Register27612.11.2.6 MPU Region Base Address Register Alias 127812.11.2.7 MPU Region Attribute and Size Register Alias 127912.11.2.8 MPU Region Base Address Register Alias 228112.11.2.9 MPU Region Attribute and Size Register Alias 228212.11.2.10 MPU Region Base Address Register Alias 328412.11.2.11 MPU Region Attribute and Size Register Alias 328512.12 Floating Point Unit (FPU)28712.12.1 Enabling the FPU28712.12.2 Floating Point Unit (FPU) User Interface28812.12.2.1 Coprocessor Access Control Register28912.12.2.2 Floating-point Context Control Register29012.12.2.3 Floating-point Context Address Register29212.12.2.4 Floating-point Status Control Register29312.12.2.5 Floating-point Default Status Control Register29512.13 Glossary29613. Debug and Test Features30113.1 Description30113.2 Embedded Characteristics30113.3 Debug and Test Block Diagram30213.4 Application Examples30313.4.1 Debug Environment30313.4.2 Test Environment30313.5 Debug and Test Pin Description30413.6 Functional Description30513.6.1 Test Pin30513.6.2 NRST Pin30513.6.3 ERASE Pin30513.6.4 Debug Architecture30513.6.5 Serial Wire JTAG Debug Port (SWJ-DP) Pins30613.6.5.1 SW-DP and JTAG-DP Selection Mechanism30713.6.6 FPB (Flash Patch Breakpoint)30713.6.7 DWT (Data Watchpoint and Trace)30713.6.8 ITM (Instrumentation Trace Macrocell)30713.6.8.1 How to Configure the ITM30813.6.8.2 Asynchronous Mode30813.6.8.3 5.4.3. How to Configure the TPIU30813.6.9 IEEE® 1149.1 JTAG Boundary Scan30813.6.9.1 JTAG Boundary-scan Register30913.6.10 ID Code Register31014. Reset Controller (RSTC)31114.1 Description31114.2 Embedded Characteristics31114.3 Block Diagram31114.4 Functional Description31214.4.1 Reset Controller Overview31214.4.2 NRST Manager31214.4.2.1 NRST Signal or Interrupt31214.4.2.2 NRST External Reset Control31314.4.3 Brownout Manager31314.4.4 Reset States31314.4.4.1 General Reset31314.4.4.2 Backup Reset31414.4.4.3 User Reset31414.4.4.4 Software Reset31414.4.4.5 Watchdog Reset31514.4.5 Reset State Priorities31614.4.6 Reset Controller Status Register31714.5 Reset Controller (RSTC) User Interface31814.5.1 Reset Controller Control Register31914.5.2 Reset Controller Status Register32014.5.3 Reset Controller Mode Register32115. Real-time Timer (RTT)32215.1 Description32215.2 Embedded Characteristics32215.3 Block Diagram32215.4 Functional Description32215.5 Real-time Timer (RTT) User Interface32515.5.1 Real-time Timer Mode Register32615.5.2 Real-time Timer Alarm Register32715.5.3 Real-time Timer Value Register32815.5.4 Real-time Timer Status Register32916. Real-time Clock (RTC)33016.1 Description33016.2 Embedded Characteristics33016.3 Block Diagram33116.4 Product Dependencies33116.4.1 Power Management33116.4.2 Interrupt33116.5 Functional Description33116.5.1 Reference Clock33116.5.2 Timing33116.5.3 Alarm33216.5.4 Error Checking when Programming33216.5.5 RTC Internal Free Running Counter Error Checking33216.5.6 Updating Time/Calendar33316.5.7 RTC Accurate Clock Calibration33516.5.8 Waveform Generation33516.6 Real-time Clock (RTC) User Interface33716.6.1 RTC Control Register33816.6.2 RTC Mode Register34016.6.3 RTC Time Register34316.6.4 RTC Calendar Register34416.6.5 RTC Time Alarm Register34516.6.6 RTC Calendar Alarm Register34616.6.7 RTC Status Register34716.6.8 RTC Status Clear Command Register34916.6.9 RTC Interrupt Enable Register35016.6.10 RTC Interrupt Disable Register35116.6.11 RTC Interrupt Mask Register35216.6.12 RTC Valid Entry Register35317. Watchdog Timer (WDT)35417.1 Description35417.2 Embedded Characteristics35417.3 Block Diagram35417.4 Functional Description35517.5 Watchdog Timer (WDT) User Interface35717.5.1 Watchdog Timer Control Register35817.5.2 Watchdog Timer Mode Register35917.5.3 Watchdog Timer Status Register36118. Reinforced Safety Watchdog Timer (RSWDT)36218.1 Description36218.2 Embedded Characteristics36218.3 Block Diagram36318.4 Functional Description36418.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface36618.5.1 Reinforced Safety Watchdog Timer Control Register36718.5.2 Reinforced Safety Watchdog Timer Mode Register36818.5.3 Reinforced Safety Watchdog Timer Status Register37019. Supply Controller (SUPC)37119.1 Description37119.2 Embedded Characteristics37119.3 Block Diagram37219.4 Supply Controller Functional Description37319.4.1 Supply Controller Overview37319.4.2 Slow Clock Generator37419.4.3 Core Voltage Regulator Control/Backup Low-power Mode37419.4.4 Supply Monitor37419.4.5 Backup Power Supply Reset37519.4.5.1 Raising the Backup Power Supply37519.4.6 Core Reset37619.4.6.1 Supply Monitor Reset37619.4.6.2 Brownout Detector Reset37719.4.7 Wake-up Sources37719.4.7.1 Force Wake-up37719.4.7.2 Wake-up Inputs37819.4.7.3 Low-power Tamper Detection and Anti-Tampering37819.4.7.4 Clock Alarms38019.4.7.5 Supply Monitor Detection38019.4.8 Register Write Protection38019.4.9 Register Bits in Backup Domain (VDDIO)38119.5 Supply Controller (SUPC) User Interface38219.5.1 System Controller (SYSC) User Interface38219.5.2 Supply Controller (SUPC) User Interface38219.5.3 Supply Controller Control Register38319.5.4 Supply Controller Supply Monitor Mode Register38419.5.5 Supply Controller Mode Register38519.5.6 Supply Controller Wake-up Mode Register38619.5.7 Supply Controller Wake-up Inputs Register38819.5.8 Supply Controller Status Register38919.5.9 System Controller Write Protection Mode Register39120. General Purpose Backup Registers (GPBR)39220.1 Description39220.2 Embedded Characteristics39220.3 General Purpose Backup Registers (GPBR) User Interface39320.3.1 General Purpose Backup Register x39421. Enhanced Embedded Flash Controller (EEFC)39521.1 Description39521.2 Embedded Characteristics39521.3 Product Dependencies39521.3.1 Power Management39521.3.2 Interrupt Sources39521.4 Functional Description39521.4.1 Embedded Flash Organization39521.4.2 Read Operations39721.4.2.1 128-bit or 64-bit Access Mode39721.4.2.2 Code Read Optimization39721.4.2.3 Code Loop Optimization39821.4.2.4 Data Read Optimization39921.4.3 Flash Commands39921.4.3.1 Get Flash Descriptor Command40121.4.3.2 Write Commands40221.4.3.3 Erase Commands40621.4.3.4 Lock Bit Protection40721.4.3.5 GPNVM Bit40821.4.3.6 Calibration Bit40821.4.3.7 Security Bit Protection40921.4.3.8 Unique Identifier40921.4.3.9 User Signature40921.5 Enhanced Embedded Flash Controller (EEFC) User Interface41121.5.1 EEFC Flash Mode Register41221.5.2 EEFC Flash Command Register41321.5.3 EEFC Flash Status Register41521.5.4 EEFC Flash Result Register41622. Fast Flash Programming Interface (FFPI)41722.1 Description41722.2 Embedded Characteristics41722.3 Parallel Fast Flash Programming41822.3.1 Device Configuration41822.3.2 Signal Names41922.3.3 Entering Programming Mode42022.3.4 Programmer Handshaking42022.3.4.1 Write Handshaking42022.3.4.2 Read Handshaking42122.3.5 Device Operations42222.3.5.1 Flash Read Command42322.3.5.2 Flash Write Command42322.3.5.3 Flash Full Erase Command42422.3.5.4 Flash Lock Commands42422.3.5.5 Flash General-purpose NVM Commands42422.3.5.6 Flash Security Bit Command42522.3.5.7 Memory Write Command42522.3.5.8 Get Version Command42623. Cortex M Cache Controller (CMCC)42723.1 Description42723.2 Embedded Characteristics42723.3 Block Diagram42823.4 Functional Description42823.4.1 Cache Operation42823.4.2 Cache Maintenance42823.4.2.1 Cache Invalidate by Line Operation42823.4.2.2 Cache Invalidate All Operation42923.4.3 Cache Performance Monitoring42923.5 Cortex M Cache Controller (CMCC) User Interface43023.5.1 Cache Controller Type Register43123.5.2 Cache Controller Configuration Register43323.5.3 Cache Controller Control Register43423.5.4 Cache Controller Status Register43523.5.5 Cache Controller Maintenance Register 043623.5.6 Cache Controller Maintenance Register 143723.5.7 Cache Controller Monitor Configuration Register43823.5.8 Cache Controller Monitor Enable Register43923.5.9 Cache Controller Monitor Control Register44023.5.10 Cache Controller Monitor Status Register44124. SAM-BA Boot Program for SAM4E Microcontrollers44224.1 Description44224.2 Embedded Characteristics44224.3 Hardware and Software Constraints44224.4 Flow Diagram44324.5 Device Initialization44324.6 SAM-BA Monitor44424.6.1 UART0 Serial Port44524.6.2 Xmodem Protocol44524.6.3 USB Device Port44524.6.3.1 Enumeration Process44624.6.3.2 Communication Endpoints44624.6.4 In Application Programming (IAP) Feature44725. Bus Matrix (MATRIX)44825.1 Description44825.2 Embedded Characteristics44825.2.1 Matrix Masters44825.2.2 Matrix Slaves44825.2.3 Master to Slave Access44925.3 Memory Mapping45025.4 Special Bus Granting Mechanism45025.5 No Default Master45025.6 Last Access Master45125.7 Fixed Default Master45125.8 Arbitration45125.8.1 Arbitration Scheduling45125.8.1.1 Undefined Length Burst Arbitration45225.8.1.2 Slot Cycle Limit Arbitration45225.8.2 Arbitration Priority Scheme45225.8.2.1 Fixed Priority Arbitration45325.8.2.2 Round-Robin Arbitration45325.9 System I/O Configuration45325.10 SMC NAND Flash Chip Select Configuration45325.11 Write Protect Registers45425.12 Bus Matrix (MATRIX) User Interface45525.12.1 Bus Matrix Master Configuration Registers45725.12.2 Bus Matrix Slave Configuration Registers45825.12.3 Bus Matrix Priority Registers A For Slaves46025.12.4 Bus Matrix Master Remap Control Register46125.12.5 System I/O Configuration Register46225.12.6 SMC NAND Flash Chip Select Configuration Register46325.12.7 Write Protect Mode Register46425.12.8 Write Protect Status Register46526. DMA Controller (DMAC)46626.1 Description46626.2 Embedded Characteristics46626.3 DMA Controller Peripheral Connections46726.4 Block Diagram46826.5 Functional Description46826.5.1 Basic Definitions46826.5.2 Memory Peripherals47126.5.3 Handshaking Interface47126.5.3.1 Software Handshaking47126.5.4 DMAC Transfer Types47226.5.4.1 Multi-buffer Transfers47226.5.4.2 Programming DMAC for Multiple Buffer Transfers47326.5.4.3 Ending Multi-buffer Transfers47426.5.5 Programming a Channel47426.5.5.1 Programming Examples47426.5.6 Disabling a Channel Prior to Transfer Completion48126.5.6.1 Abnormal Transfer Termination48226.6 DMAC Software Requirements48226.7 Write Protection Registers48426.8 DMA Controller (DMAC) User Interface48526.8.1 DMAC Global Configuration Register48626.8.2 DMAC Enable Register48726.8.3 DMAC Software Single Request Register48826.8.4 DMAC Software Chunk Transfer Request Register48926.8.5 DMAC Software Last Transfer Flag Register49026.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register49126.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register49226.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register49326.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register49426.8.10 DMAC Channel Handler Enable Register49526.8.11 DMAC Channel Handler Disable Register49626.8.12 DMAC Channel Handler Status Register49726.8.13 DMAC Channel x [x = 0..3] Source Address Register49826.8.14 DMAC Channel x [x = 0..3] Destination Address Register49926.8.15 DMAC Channel x [x = 0..3] Descriptor Address Register50026.8.16 DMAC Channel x [x = 0..3] Control A Register50126.8.17 DMAC Channel x [x = 0..3] Control B Register50226.8.18 DMAC Channel x [x = 0..3] Configuration Register50426.8.19 DMAC Write Protect Mode Register50626.8.20 DMAC Write Protect Status Register50727. Peripheral DMA Controller (PDC)50827.1 Description50827.2 Embedded Characteristics50827.3 Peripheral DMA Controller Connections50927.3.1 Peripheral DMA Controller 0 (PDC0)50927.3.2 Peripheral DMA Controller 1 (PDC1)51027.4 Block Diagram51127.5 Functional Description51227.5.1 Configuration51227.5.2 Memory Pointers51227.5.3 Transfer Counters51227.5.4 Data Transfers51327.5.5 PDC Flags and Peripheral Status Register51327.5.5.1 Receive Transfer End51327.5.5.2 Transmit Transfer End51327.5.5.3 Receive Buffer Full51327.5.5.4 Transmit Buffer Empty51327.6 Peripheral DMA Controller (PDC) User Interface51427.6.1 Receive Pointer Register51527.6.2 Receive Counter Register51627.6.3 Transmit Pointer Register51727.6.4 Transmit Counter Register51827.6.5 Receive Next Pointer Register51927.6.6 Receive Next Counter Register52027.6.7 Transmit Next Pointer Register52127.6.8 Transmit Next Counter Register52227.6.9 Transfer Control Register52327.6.10 Transfer Status Register52428. Static Memory Controller (SMC)52528.1 Description52528.2 Embedded Characteristics52528.3 I/O Lines Description52628.4 Product Dependencies52628.4.1 I/O Lines52628.4.2 Power Management52628.5 External Memory Mapping52628.6 Connection to External Devices52728.6.1 Data Bus Width52728.6.1.1 NAND Flash Support52728.7 Application Example52928.7.1 Implementation Examples52928.7.1.1 8-bit NAND Flash53028.7.1.2 NOR Flash53128.8 Standard Read and Write Protocols53128.8.1 Read Waveforms53128.8.1.1 NRD Waveform53228.8.1.2 NCS Waveform53228.8.1.3 Read Cycle53228.8.1.4 Null Delay Setup and Hold53328.8.1.5 Null Pulse53328.8.2 Read Mode53328.8.2.1 Read is Controlled by NRD (READ_MODE = 1):53328.8.2.2 Read is Controlled by NCS (READ_MODE = 0)53428.8.3 Write Waveforms53528.8.3.1 NWE Waveforms53528.8.3.2 NCS Waveforms53528.8.3.3 Write Cycle53528.8.3.4 Null Delay Setup and Hold53628.8.3.5 Null Pulse53628.8.4 Write Mode53628.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):53628.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)53728.8.5 Write Protected Registers53728.8.6 Coding Timing Parameters53828.8.7 Reset Values of Timing Parameters53828.8.8 Usage Restriction53828.9 Scrambling/Unscrambling Function53928.10 Automatic Wait States53928.10.1 Chip Select Wait States53928.10.2 Early Read Wait State54028.10.3 Reload User Configuration Wait State54228.10.3.1 User Procedure54228.10.3.2 Slow Clock Mode Transition54328.10.4 Read to Write Wait State54328.11 Data Float Wait States54428.11.1 READ_MODE54428.11.2 TDF Optimization Enabled (TDF_MODE = 1)54528.11.3 TDF Optimization Disabled (TDF_MODE = 0)54628.12 External Wait54828.12.1 Restriction54828.12.2 Frozen Mode54928.12.3 Ready Mode55128.12.4 NWAIT Latency and Read/Write Timings55328.13 Slow Clock Mode55428.13.1 Slow Clock Mode Waveforms55428.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode55528.14 Asynchronous Page Mode55628.14.1 Protocol and Timings in Page Mode55628.14.2 Page Mode Restriction55728.14.3 Sequential and Non-sequential Accesses55728.15 Static Memory Controller (SMC) User Interface55928.15.1 SMC Setup Register56028.15.2 SMC Pulse Register56128.15.3 SMC Cycle Register56228.15.4 SMC MODE Register56328.15.5 SMC OCMS Mode Register56528.15.6 SMC OCMS Key1 Register56628.15.7 SMC OCMS Key2 Register56728.15.8 SMC Write Protect Mode Register56828.15.9 SMC Write Protect Status Register56929. Clock Generator57029.1 Description57029.2 Embedded Characteristics57029.3 Block Diagram57129.4 Slow Clock57229.4.1 Slow Clock RC Oscillator57329.4.2 Slow Clock Crystal Oscillator57429.5 Main Clock57529.5.1 Fast RC Oscillator57629.5.2 Fast RC Oscillator Clock Frequency Adjustment57729.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator57829.5.4 Main Clock Oscillator Selection57929.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator58029.5.6 Software Sequence to Detect the Presence of Fast Crystal58129.5.7 Main Clock Frequency Counter58229.6 Divider and PLL Block58329.6.1 Divider and Phase Lock Loop Programming58430. Power Management Controller (PMC)58530.1 Description58530.2 Embedded Characteristics58530.3 Block Diagram58630.4 Master Clock Controller58630.5 Processor Clock Controller58730.6 SysTick Clock58730.7 USB Clock Controller58730.8 Peripheral Clock Controller58830.9 Free-Running Processor Clock58830.10 Programmable Clock Output Controller58830.11 Fast Startup58830.12 Startup from Embedded Flash59030.13 Main Clock Failure Detector59030.14 Programming Sequence59130.15 Clock Switching Details59430.15.1 Master Clock Switching Timings59430.15.2 Clock Switching Waveforms59530.16 Register Write Protection59730.17 Power Management Controller (PMC) User Interface59830.17.1 PMC System Clock Enable Register60030.17.2 PMC System Clock Disable Register60130.17.3 PMC System Clock Status Register60230.17.4 PMC Peripheral Clock Enable Register 060330.17.5 PMC Peripheral Clock Disable Register 060430.17.6 PMC Peripheral Clock Status Register 060530.17.7 PMC Clock Generator Main Oscillator Register60630.17.8 PMC Clock Generator Main Clock Frequency Register60830.17.9 PMC Clock Generator PLLA Register60930.17.10 PMC Master Clock Register61030.17.11 PMC USB Clock Register61130.17.12 PMC Programmable Clock Register61230.17.13 PMC Interrupt Enable Register61330.17.14 PMC Interrupt Disable Register61430.17.15 PMC Status Register61530.17.16 PMC Interrupt Mask Register61730.17.17 PMC Fast Startup Mode Register61830.17.18 PMC Fast Startup Polarity Register61930.17.19 PMC Fault Output Clear Register62030.17.20 PMC Write Protection Mode Register62130.17.21 PMC Write Protection Status Register62230.17.22 PMC Peripheral Clock Enable Register 162330.17.23 PMC Peripheral Clock Disable Register 162430.17.24 PMC Peripheral Clock Status Register 162530.17.25 PMC Oscillator Calibration Register62630.17.26 PLL Maximum Multiplier Value Register62731. Advanced Encryption Standard (AES)62831.1 Description62831.2 Embedded Characteristics62831.3 Product Dependencies62931.3.1 Power Management62931.3.2 Interrupt62931.4 Functional Description62931.4.1 Operation Modes62931.4.2 Double Input Buffer63031.4.3 Start Modes63031.4.3.1 Manual Mode63031.4.3.2 Auto Mode63131.4.3.3 DMA Mode63131.4.4 Last Output Data Mode63131.4.4.1 Manual and Auto Modes63231.4.4.2 DMA Mode63231.5 Security Features63431.5.1 Unspecified Register Access Detection63431.6 Advanced Encryption Standard (AES) User Interface63531.6.1 AES Control Register63631.6.2 AES Mode Register63731.6.3 AES Interrupt Enable Register64031.6.4 AES Interrupt Disable Register64131.6.5 AES Interrupt Mask Register64231.6.6 AES Interrupt Status Register64331.6.7 AES Key Word Register x64431.6.8 AES Input Data Register x64531.6.9 AES Output Data Register x64631.6.10 AES Initialization Vector Register x64732. Chip Identifier (CHIPID)64832.1 Description64832.2 Embedded Characteristics64832.3 Chip Identifier (CHIPID) User Interface64932.3.1 Chip ID Register65032.3.2 Chip ID Extension Register65333. Controller Area Network (CAN)65433.1 Description65433.2 Embedded Characteristics65433.3 Block Diagram65533.4 Application Block Diagram65633.5 I/O Lines Description65633.6 Product Dependencies65633.6.1 I/O Lines65633.6.2 Power Management65633.6.3 Interrupt65733.7 CAN Controller Features65733.7.1 CAN Protocol Overview65733.7.2 Mailbox Organization65733.7.2.1 Message Acceptance Procedure65733.7.2.2 Receive Mailbox65833.7.2.3 Transmit Mailbox65933.7.3 Time Management Unit66033.7.4 CAN 2.0 Standard Features66033.7.4.1 CAN Bit Timing Configuration660CAN Bus Synchronization663Autobaud Mode66433.7.4.2 Error Detection664Fault Confinement665Error Interrupt Handler66533.7.4.3 Overload66633.7.5 Low-power Mode66633.7.5.1 Enabling Low-power Mode66633.7.5.2 Disabling Low-power Mode66733.8 Functional Description66833.8.1 CAN Controller Initialization66833.8.2 CAN Controller Interrupt Handling66933.8.3 CAN Controller Message Handling67033.8.3.1 Receive Handling670Simple Receive Mailbox670Receive with Overwrite Mailbox671Chaining Mailboxes67133.8.3.2 Transmission Handling67333.8.3.3 Remote Frame Handling674Producer Configuration675Consumer Configuration67533.8.4 CAN Controller Timing Modes67633.8.4.1 Timestamping Mode67633.8.4.2 Time Triggered Mode677Synchronization by a Reference Message677Transmitting within a Time Window677Freezing the Internal Timer Counter67733.8.5 Write Protected Registers67933.9 Controller Area Network (CAN) User Interface68033.9.1 CAN Mode Register68133.9.2 CAN Interrupt Enable Register68333.9.3 CAN Interrupt Disable Register68533.9.4 CAN Interrupt Mask Register68733.9.5 CAN Status Register68933.9.6 CAN Baudrate Register69233.9.7 CAN Timer Register69333.9.8 CAN Timestamp Register69433.9.9 CAN Error Counter Register69533.9.10 CAN Transfer Command Register69633.9.11 CAN Abort Command Register69733.9.12 CAN Write Protection Mode Register69833.9.13 CAN Write Protection Status Register69933.9.14 CAN Message Mode Register70033.9.15 CAN Message Acceptance Mask Register70133.9.16 CAN Message ID Register70233.9.17 CAN Message Family ID Register70333.9.18 CAN Message Status Register70433.9.19 CAN Message Data Low Register70733.9.20 CAN Message Data High Register70833.9.21 CAN Message Control Register70934. Parallel Input/Output Controller (PIO)71134.1 Description71134.2 Embedded Characteristics71234.3 Block Diagram71334.4 Product Dependencies71534.4.1 Pin Multiplexing71534.4.2 External Interrupt Lines71534.4.3 Power Management71534.4.4 Interrupt Generation71534.5 Functional Description71634.5.1 Pull-up and Pull-down Resistor Control71634.5.2 I/O Line or Peripheral Function Selection71734.5.3 Peripheral A or B or C or D Selection71734.5.4 Output Control71834.5.5 Synchronous Data Output71834.5.6 Multi-Drive Control (Open Drain)71834.5.7 Output Line Timings71834.5.8 Inputs71934.5.9 Input Glitch and Debouncing Filters71934.5.10 Input Edge/Level Interrupt72034.5.11 I/O Lines Lock72334.5.12 Programmable I/O Delays72334.5.13 Programmable Schmitt Trigger72434.5.14 Parallel Capture Mode72434.5.14.1 Overview72434.5.14.2 Functional Description72434.5.14.3 Restrictions72734.5.14.4 Programming Sequence727Without PDC727With PDC72734.5.15 I/O Lines Programming Example72834.5.16 Register Write Protection72934.6 Parallel Input/Output Controller (PIO) User Interface73034.6.1 PIO Enable Register73334.6.2 PIO Disable Register73434.6.3 PIO Status Register73534.6.4 PIO Output Enable Register73634.6.5 PIO Output Disable Register73734.6.6 PIO Output Status Register73834.6.7 PIO Input Filter Enable Register73934.6.8 PIO Input Filter Disable Register74034.6.9 PIO Input Filter Status Register74134.6.10 PIO Set Output Data Register74234.6.11 PIO Clear Output Data Register74334.6.12 PIO Output Data Status Register74434.6.13 PIO Pin Data Status Register74534.6.14 PIO Interrupt Enable Register74634.6.15 PIO Interrupt Disable Register74734.6.16 PIO Interrupt Mask Register74834.6.17 PIO Interrupt Status Register74934.6.18 PIO Multi-driver Enable Register75034.6.19 PIO Multi-driver Disable Register75134.6.20 PIO Multi-driver Status Register75234.6.21 PIO Pull-Up Disable Register75334.6.22 PIO Pull-Up Enable Register75434.6.23 PIO Pull-Up Status Register75534.6.24 PIO Peripheral ABCD Select Register 175634.6.25 PIO Peripheral ABCD Select Register 275734.6.26 PIO Input Filter Slow Clock Disable Register75834.6.27 PIO Input Filter Slow Clock Enable Register75934.6.28 PIO Input Filter Slow Clock Status Register76034.6.29 PIO Slow Clock Divider Debouncing Register76134.6.30 PIO Pad Pull-Down Disable Register76234.6.31 PIO Pad Pull-Down Enable Register76334.6.32 PIO Pad Pull-Down Status Register76434.6.33 PIO Output Write Enable Register76534.6.34 PIO Output Write Disable Register76634.6.35 PIO Output Write Status Register76734.6.36 PIO Additional Interrupt Modes Enable Register76834.6.37 PIO Additional Interrupt Modes Disable Register76934.6.38 PIO Additional Interrupt Modes Mask Register77034.6.39 PIO Edge Select Register77134.6.40 PIO Level Select Register77234.6.41 PIO Edge/Level Status Register77334.6.42 PIO Falling Edge/Low-Level Select Register77434.6.43 PIO Rising Edge/High-Level Select Register77534.6.44 PIO Fall/Rise - Low/High Status Register77634.6.45 PIO Lock Status Register77734.6.46 PIO Write Protection Mode Register77834.6.47 PIO Write Protection Status Register77934.6.48 PIO Schmitt Trigger Register78034.6.49 PIO I/O Delay Register78134.6.50 PIO Parallel Capture Mode Register78234.6.51 PIO Parallel Capture Interrupt Enable Register78334.6.52 PIO Parallel Capture Interrupt Disable Register78434.6.53 PIO Parallel Capture Interrupt Mask Register78534.6.54 PIO Parallel Capture Interrupt Status Register78634.6.55 PIO Parallel Capture Reception Holding Register78735. Serial Peripheral Interface (SPI)78835.1 Description78835.2 Embedded Characteristics78935.3 Block Diagram79035.4 Application Block Diagram79135.5 Signal Description79135.6 Product Dependencies79135.6.1 I/O Lines79135.6.2 Power Management79235.6.3 Interrupt79235.6.4 Peripheral DMA Controller (PDC) or Direct Memory Access Controller (DMAC)79235.7 Functional Description79235.7.1 Modes of Operation79235.7.2 Data Transfer79335.7.3 Master Mode Operations79435.7.3.1 Master Mode Block Diagram79535.7.3.2 Master Mode Flow Diagram79635.7.3.3 Clock Generation79835.7.3.4 Transfer Delays79835.7.3.5 Peripheral Selection79935.7.3.6 SPI Peripheral DMA Controller (PDC)79935.7.3.7 SPI Direct Access Memory Controller (DMAC)80035.7.3.8 Peripheral Chip Select Decoding80035.7.3.9 Peripheral Deselection without DMA nor PDC80135.7.3.10 Peripheral Deselection with DMA or PDC80235.7.3.11 Mode Fault Detection80335.7.4 SPI Slave Mode80435.7.5 Register Write Protection80535.8 Serial Peripheral Interface (SPI) User Interface80635.8.1 SPI Control Register80735.8.2 SPI Mode Register80835.8.3 SPI Receive Data Register81035.8.4 SPI Transmit Data Register81135.8.5 SPI Status Register81235.8.6 SPI Interrupt Enable Register81435.8.7 SPI Interrupt Disable Register81535.8.8 SPI Interrupt Mask Register81635.8.9 SPI Chip Select Register81735.8.10 SPI Write Protection Mode Register82035.8.11 SPI Write Protection Status Register82136. Two-wire Interface (TWI)82236.1 Description82236.2 Embedded Characteristics82236.3 List of Abbreviations82336.4 Block Diagram82336.5 Application Block Diagram82436.5.1 I/O Lines Description82436.6 Product Dependencies82436.6.1 I/O Lines82436.6.2 Power Management82436.6.3 Interrupt82536.7 Functional Description82536.7.1 Transfer Format82536.7.2 Modes of Operation82536.7.3 Master Mode82636.7.3.1 Definition82636.7.3.2 Application Block Diagram82636.7.3.3 Programming Master Mode82636.7.3.4 Master Transmitter Mode82636.7.3.5 Master Receiver Mode82836.7.3.6 Internal Address82936.7.3.7 Using the Peripheral DMA Controller (PDC)83136.7.3.8 SMBus Quick Command (Master Mode Only)83236.7.3.9 Read/Write Flowcharts83236.7.4 Multi-master Mode83936.7.4.1 Definition83936.7.4.2 Different Multi-master Modes83936.7.5 Slave Mode84236.7.5.1 Definition84236.7.5.2 Application Block Diagram84236.7.5.3 Programming Slave Mode84236.7.5.4 Receiving Data84236.7.5.5 Data Transfer84336.7.5.6 Using the Peripheral DMA Controller (PDC) in Slave Mode84736.7.5.7 Read Write Flowcharts84736.7.6 Register Write Protection84836.8 Two-wire Interface (TWI) User Interface84936.8.1 TWI Control Register85036.8.2 TWI Master Mode Register85236.8.3 TWI Slave Mode Register85336.8.4 TWI Internal Address Register85436.8.5 TWI Clock Waveform Generator Register85536.8.6 TWI Status Register85636.8.7 TWI Interrupt Enable Register85936.8.8 TWI Interrupt Disable Register86036.8.9 TWI Interrupt Mask Register86136.8.10 TWI Receive Holding Register86236.8.11 TWI Transmit Holding Register86336.8.12 TWI Write Protection Mode Register86436.8.13 TWI Write Protection Status Register86537. Universal Asynchronous Receiver Transmitter (UART)86637.1 Description86637.2 Embedded Characteristics86637.3 Block Diagram86637.4 Product Dependencies86737.4.1 I/O Lines86737.4.2 Power Management86737.4.3 Interrupt Source86737.5 UART Operations86737.5.1 Baud Rate Generator86737.5.2 Receiver86837.5.2.1 Receiver Reset, Enable and Disable86837.5.2.2 Start Detection and Data Sampling86837.5.2.3 Receiver Ready86937.5.2.4 Receiver Overrun86937.5.2.5 Parity Error86937.5.2.6 Receiver Framing Error87037.5.3 Transmitter87037.5.3.1 Transmitter Reset, Enable and Disable87037.5.3.2 Transmit Format87037.5.3.3 Transmitter Control87137.5.4 Peripheral DMA Controller (PDC)87137.5.5 Register Write Protection87237.5.6 Test Modes87237.6 Universal Asynchronous Receiver Transmitter (UART) User Interface87337.6.1 UART Control Register87437.6.2 UART Mode Register87537.6.3 UART Interrupt Enable Register87637.6.4 UART Interrupt Disable Register87737.6.5 UART Interrupt Mask Register87837.6.6 UART Status Register87937.6.7 UART Receiver Holding Register88137.6.8 UART Transmit Holding Register88237.6.9 UART Baud Rate Generator Register88337.6.10 UART Write Protection Mode Register88438. Universal Synchronous Asynchronous Receiver Transmitter (USART)88538.1 Description88538.2 Embedded Characteristics88538.3 Block Diagram88638.4 Application Block Diagram88738.5 I/O Lines Description88838.6 Product Dependencies88938.6.1 I/O Lines88938.6.2 Power Management88938.6.3 Interrupt88938.7 Functional Description89038.7.1 Baud Rate Generator89038.7.1.1 Baud Rate in Asynchronous Mode890Baud Rate Calculation Example89138.7.1.2 Fractional Baud Rate in Asynchronous Mode89138.7.1.3 Baud Rate in Synchronous Mode or SPI Mode89238.7.1.4 Baud Rate in ISO 7816 Mode89238.7.2 Receiver and Transmitter Control89438.7.3 Synchronous and Asynchronous Modes89438.7.3.1 Transmitter Operations89438.7.3.2 Manchester Encoder895Drift Compensation89738.7.3.3 Asynchronous Receiver89738.7.3.4 Manchester Decoder89838.7.3.5 Radio Interface: Manchester Encoded USART Application90038.7.3.6 Synchronous Receiver90138.7.3.7 Receiver Operations90238.7.3.8 Parity90238.7.3.9 Multidrop Mode90338.7.3.10 Transmitter Timeguard90338.7.3.11 Receiver Time-out90438.7.3.12 Framing Error90638.7.3.13 Transmit Break90638.7.3.14 Receive Break90738.7.3.15 Hardware Handshaking90738.7.4 ISO7816 Mode90838.7.4.1 ISO7816 Mode Overview90838.7.4.2 Protocol T = 0909Receive Error Counter909Receive NACK Inhibit909Transmit Character Repetition909Disable Successive Receive NACK91038.7.4.3 Protocol T = 191038.7.5 IrDA Mode91038.7.5.1 IrDA Modulation91138.7.5.2 IrDA Baud Rate91138.7.5.3 IrDA Demodulator91238.7.6 RS485 Mode91238.7.7 Modem Mode91438.7.8 SPI Mode91538.7.8.1 Modes of Operation91538.7.8.2 Baud Rate91538.7.8.3 Data Transfer91638.7.8.4 Receiver and Transmitter Control91738.7.8.5 Character Transmission91738.7.8.6 Character Reception91838.7.8.7 Receiver Timeout91838.7.9 Test Modes91838.7.9.1 Normal Mode91838.7.9.2 Automatic Echo Mode91938.7.9.3 Local Loopback Mode91938.7.9.4 Remote Loopback Mode91938.7.10 Register Write Protection92038.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface92138.8.1 USART Control Register92238.8.2 USART Control Register (SPI_MODE)92538.8.3 USART Mode Register92738.8.4 USART Mode Register (SPI_MODE)93038.8.5 USART Interrupt Enable Register93238.8.6 USART Interrupt Enable Register (SPI_MODE)93438.8.7 USART Interrupt Disable Register93538.8.8 USART Interrupt Disable Register (SPI_MODE)93738.8.9 USART Interrupt Mask Register93838.8.10 USART Interrupt Mask Register (SPI_MODE)94038.8.11 USART Channel Status Register94138.8.12 USART Channel Status Register (SPI_MODE)94438.8.13 USART Receive Holding Register94538.8.14 USART Transmit Holding Register94638.8.15 USART Baud Rate Generator Register94738.8.16 USART Receiver Time-out Register94838.8.17 USART Transmitter Timeguard Register94938.8.18 USART FI DI RATIO Register95038.8.19 USART Number of Errors Register95138.8.20 USART IrDA FILTER Register95238.8.21 USART Manchester Configuration Register95338.8.22 USART Write Protection Mode Register95538.8.23 USART Write Protection Status Register95639. Timer Counter (TC)95739.1 Description95739.2 Embedded Characteristics95739.3 Block Diagram95839.4 Pin Name List95939.5 Product Dependencies95939.5.1 I/O Lines95939.5.2 Power Management96039.5.3 Interrupt96039.5.4 Synchronization Inputs from PWM96039.5.5 Fault Output96039.6 Functional Description96039.6.1 TC Description96039.6.2 32-bit Counter96039.6.3 Clock Selection96139.6.4 Clock Control96239.6.5 TC Operating Modes96339.6.6 Trigger96339.6.7 Capture Operating Mode96439.6.8 Capture Registers A and B96439.6.9 Transfer with PDC96439.6.10 Trigger Conditions96539.6.11 Waveform Operating Mode96739.6.12 Waveform Selection96739.6.12.1 WAVSEL = 0096939.6.12.2 WAVSEL = 1097039.6.12.3 WAVSEL = 0197139.6.12.4 WAVSEL = 1197239.6.13 External Event/Trigger Conditions97339.6.14 Synchronization with PWM97339.6.15 Output Controller97439.6.16 Quadrature Decoder Logic97539.6.16.1 Description97539.6.16.2 Input Pre-processing97639.6.16.3 Direction Status and Change Detection97939.6.16.4 Position and Rotation Measurement98039.6.16.5 Speed Measurement98139.6.16.6 Missing Pulse Detection and Auto-correction98139.6.17 2-bit Gray Up/Down Counter for Stepper Motor98239.6.18 Register Write Protection98239.6.19 Fault Mode98239.7 Timer Counter (TC) User Interface98439.7.1 TC Channel Control Register98539.7.2 TC Channel Mode Register: Capture Mode98639.7.3 TC Channel Mode Register: Waveform Mode98939.7.4 TC Stepper Motor Mode Register99339.7.5 TC Register AB99439.7.6 TC Counter Value Register99539.7.7 TC Register A99639.7.8 TC Register B99739.7.9 TC Register C99839.7.10 TC Status Register99939.7.11 TC Interrupt Enable Register100139.7.12 TC Interrupt Disable Register100339.7.13 TC Interrupt Mask Register100539.7.14 TC Extended Mode Register100739.7.15 TC Block Control Register100839.7.16 TC Block Mode Register100939.7.17 TC QDEC Interrupt Enable Register101139.7.18 TC QDEC Interrupt Disable Register101239.7.19 TC QDEC Interrupt Mask Register101339.7.20 TC QDEC Interrupt Status Register101439.7.21 TC Fault Mode Register101539.7.22 TC Write Protection Mode Register101640. Pulse Width Modulation Controller (PWM)101740.1 Description101740.2 Embedded Characteristics101840.3 Block Diagram101940.4 I/O Lines Description101940.5 Product Dependencies102040.5.1 I/O Lines102040.5.2 Power Management102140.5.3 Interrupt Sources102140.5.4 Fault Inputs102140.6 Functional Description102340.6.1 PWM Clock Generator102340.6.2 PWM Channel102440.6.2.1 Channel Block Diagram102440.6.2.2 Comparator102540.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor102740.6.2.4 Dead-Time Generator102840.6.2.5 Output Override102940.6.2.6 Fault Protection103040.6.2.7 Spread Spectrum Counter103240.6.2.8 Additional Edges103240.6.2.9 Synchronous Channels103340.6.2.10 Update Time for Double-Buffering Registers103940.6.3 PWM Comparison Units104040.6.4 PWM Event Lines104140.6.5 PWM Controller Operations104240.6.5.1 Initialization104240.6.5.2 Source Clock Selection Criteria104340.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times104340.6.5.4 Changing the Synchronous Channels Update Period104440.6.5.5 Changing the Comparison Value and the Comparison Configuration104540.6.5.6 Interrupts104640.6.6 Register Write Protection104640.7 Pulse Width Modulation Controller (PWM) User Interface104840.7.1 PWM Clock Register105140.7.2 PWM Enable Register105240.7.3 PWM Disable Register105340.7.4 PWM Status Register105440.7.5 PWM Interrupt Enable Register 1105540.7.6 PWM Interrupt Disable Register 1105640.7.7 PWM Interrupt Mask Register 1105740.7.8 PWM Interrupt Status Register 1105840.7.9 PWM Sync Channels Mode Register105940.7.10 PWM DMA Register106040.7.11 PWM Sync Channels Update Control Register106140.7.12 PWM Sync Channels Update Period Register106240.7.13 PWM Sync Channels Update Period Update Register106340.7.14 PWM Interrupt Enable Register 2106440.7.15 PWM Interrupt Disable Register 2106540.7.16 PWM Interrupt Mask Register 2106640.7.17 PWM Interrupt Status Register 2106740.7.18 PWM Output Override Value Register106840.7.19 PWM Output Selection Register106940.7.20 PWM Output Selection Set Register107040.7.21 PWM Output Selection Clear Register107140.7.22 PWM Output Selection Set Update Register107240.7.23 PWM Output Selection Clear Update Register107340.7.24 PWM Fault Mode Register10740: The fault y is active until the fault condition is removed at the peripheral(1) level.10741: The fault y stays active until the fault condition is removed at the peripheral(1) level AND until it is cleared in the PWM Fault Clear Register.10740: The fault input y is not filtered.10741: The fault input y is filtered.107440.7.25 PWM Fault Status Register10750: The current sampled value of the fault input y is 0 (after filtering if enabled).10751: The current sampled value of the fault input y is 1 (after filtering if enabled).10750: The fault y is not currently active.10751: The fault y is currently active.107540.7.26 PWM Fault Clear Register10760: No effect.10761: If bit y of FMOD field is set to ‘1’ and if the fault input y is not at the level defined by the bit y of FPOL field, the fault y is cleared and becomes inactive (FMOD and FPOL fields belong to PWM Fault Mode Register), else writing this bit t...107640.7.27 PWM Fault Protection Value Register 1107740.7.28 PWM Fault Protection Enable Register10780: Fault y is not used for the fault protection of channel x.10781: Fault y is used for the fault protection of channel x.107840.7.29 PWM Event Line x Register107940.7.30 PWM Spread Spectrum Register108040.7.31 PWM Spread Spectrum Update Register108140.7.32 PWM Stepper Motor Mode Register108240.7.33 PWM Fault Protection Value Register 2108340.7.34 PWM Write Protection Control Register108440.7.35 PWM Write Protection Status Register108540.7.36 PWM Comparison x Value Register108640.7.37 PWM Comparison x Value Update Register108740.7.38 PWM Comparison x Mode Register108840.7.39 PWM Comparison x Mode Update Register108940.7.40 PWM Channel Mode Register109040.7.41 PWM Channel Duty Cycle Register109240.7.42 PWM Channel Duty Cycle Update Register109340.7.43 PWM Channel Period Register109440.7.44 PWM Channel Period Update Register109540.7.45 PWM Channel Counter Register109640.7.46 PWM Channel Dead Time Register109740.7.47 PWM Channel Dead Time Update Register109840.7.48 PWM Channel Mode Update Register109940.7.49 PWM Channel Additional Edge Register110040.7.50 PWM Channel Additional Edge Update Register110141. High Speed MultiMedia Card Interface (HSMCI)110241.1 Description110241.2 Embedded Characteristics110241.3 Block Diagram110341.4 Application Block Diagram110441.5 Pin Name List110441.6 Product Dependencies110541.6.1 I/O Lines110541.6.2 Power Management110541.6.3 Interrupt110541.7 Bus Topology110541.8 High Speed MultiMedia Card Operations110741.8.1 Command - Response Operation110841.8.2 Data Transfer Operation111141.8.3 Read Operation111141.8.4 Write Operation111341.9 SD/SDIO Card Operation111641.9.1 SDIO Data Transfer Type111641.9.2 SDIO Interrupts111641.10 CE-ATA Operation111641.10.1 Executing an ATA Polling Command111741.10.2 Executing an ATA Interrupt Command111741.10.3 Aborting an ATA Command111741.10.4 CE-ATA Error Recovery111741.11 HSMCI Boot Operation Mode111841.11.1 Boot Procedure, Processor Mode111841.12 HSMCI Transfer Done Timings111841.12.1 Definition111841.12.2 Read Access111841.12.3 Write Access111941.13 Register Write Protection112041.14 High Speed MultiMedia Card Interface (HSMCI) User Interface112141.14.1 HSMCI Control Register112241.14.2 HSMCI Mode Register112341.14.3 HSMCI Data Timeout Register112541.14.4 HSMCI SDCard/SDIO Register112641.14.5 HSMCI Argument Register112741.14.6 HSMCI Command Register112841.14.7 HSMCI Block Register113041.14.8 HSMCI Completion Signal Timeout Register113141.14.9 HSMCI Response Register113241.14.10 HSMCI Receive Data Register113341.14.11 HSMCI Transmit Data Register113441.14.12 HSMCI Status Register113541.14.13 HSMCI Interrupt Enable Register113941.14.14 HSMCI Interrupt Disable Register114141.14.15 HSMCI Interrupt Mask Register114341.14.16 HSMCI Configuration Register114541.14.17 HSMCI Write Protection Mode Register114641.14.18 HSMCI Write Protection Status Register114742. USB Device Port (UDP)114842.1 Description114842.2 Embedded Characteristics114842.3 Block Diagram114942.3.1 Signal Description114942.4 Product Dependencies114942.4.1 I/O Lines115042.4.2 Power Management115042.4.3 Interrupt115042.5 Typical Connection115142.5.1 USB Device Transceiver115142.5.2 VBUS Monitoring115142.6 Functional Description115242.6.1 USB 2.0 Full-speed Introduction115242.6.1.1 USB 2.0 Full-speed Transfer Types115242.6.1.2 USB Bus Transactions115242.6.1.3 USB Transfer Event Definitions115342.6.2 Handling Transactions with USB 2.0 Device Peripheral115442.6.2.1 Setup Transaction115442.6.2.2 Data IN Transaction1154Using Endpoints Without Ping-pong Attributes1154Using Endpoints With Ping-pong Attribute115542.6.2.3 Data OUT Transaction1157Data OUT Transaction Without Ping-pong Attributes1157Using Endpoints With Ping-pong Attributes115842.6.2.4 Stall Handshake116042.6.2.5 Transmit Data Cancellation1161Endpoints Without Dual-Banks1161Endpoints With Dual-Banks116142.6.3 Controlling Device States116242.6.3.1 Not Powered State116242.6.3.2 Entering Attached State116342.6.3.3 From Powered State to Default State116342.6.3.4 From Default State to Address State116342.6.3.5 From Address State to Configured State116342.6.3.6 Entering in Suspend State116342.6.3.7 Receiving a Host Resume116442.6.3.8 Sending a Device Remote Wakeup116442.7 USB Device Port (UDP) User Interface116542.7.1 UDP Frame Number Register116642.7.2 UDP Global State Register116742.7.3 UDP Function Address Register116942.7.4 UDP Interrupt Enable Register117042.7.5 UDP Interrupt Disable Register117242.7.6 UDP Interrupt Mask Register117442.7.7 UDP Interrupt Status Register117642.7.8 UDP Interrupt Clear Register117842.7.9 UDP Reset Endpoint Register117942.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK)118042.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS)118542.7.12 UDP FIFO Data Register118942.7.13 UDP Transceiver Control Register119043. Ethernet MAC (GMAC)119143.1 Description119143.2 Embedded Characteristics119143.3 Block Diagram119243.4 Signal Interface119343.5 Functional Description119343.5.1 Media Access Controller119343.5.2 1588 Time Stamp Unit119443.5.3 AHB Direct Memory Access Interface119443.5.3.1 Receive AHB Buffers119443.5.3.2 Transmit AHB Buffers119743.5.3.3 DMA Bursting on the AHB119943.5.4 MAC Transmit Block119943.5.5 MAC Receive Block120043.5.6 Checksum Offload for IP, TCP and UDP120143.5.6.1 Receiver Checksum Offload120143.5.7 MAC Filtering Block120143.5.8 Broadcast Address120343.5.9 Hash Addressing120343.5.10 Copy all Frames (Promiscuous Mode)120343.5.11 Disable Copy of Pause Frames120343.5.12 VLAN Support120443.5.13 IEEE 1588 Support120443.5.14 Time Stamp Unit120843.5.15 MAC 802.3 Pause Frame Support120943.5.15.1 802.3 Pause Frame Reception120943.5.15.2 802.3 Pause Frame Transmission121043.5.16 MAC PFC Priority-based Pause Frame Support121143.5.16.1 PFC Pause Frame Reception121143.5.16.2 PFC Pause Frame Transmission121143.5.17 PHY Interface121243.5.18 10/100 Operation121243.5.19 Jumbo Frames121243.6 Programming Interface121343.6.1 Initialization121343.6.1.1 Configuration121343.6.1.2 Receive Buffer List121343.6.1.3 Transmit Buffer List121443.6.1.4 Address Matching121443.6.1.5 PHY Maintenance121443.6.1.6 Interrupts121443.6.1.7 Transmitting Frames121543.6.1.8 Receiving Frames121543.6.2 Statistics Registers121543.7 Ethernet MAC (GMAC) User Interface121743.7.1 Network Control Register122043.7.2 Network Configuration Register122243.7.3 Network Status Register122543.7.4 User Register122643.7.5 DMA Configuration Register122743.7.6 Transmit Status Register122943.7.7 Receive Buffer Queue Base Address Register123143.7.8 Transmit Buffer Queue Base Address Register123243.7.9 Receive Status Register123343.7.10 Interrupt Status Register123443.7.11 Interrupt Enable Register123643.7.12 Interrupt Disable Register123843.7.13 Interrupt Mask Register124043.7.14 PHY Maintenance Register124543.7.15 Receive Pause Quantum Register124743.7.16 Transmit Pause Quantum Register124843.7.17 Hash Register Bottom [31:0]124943.7.18 Hash Register Top [63:32]125043.7.19 Specific Address 1 Bottom [31:0] Register125143.7.20 Specific Address 1 Top [47:32] Register125243.7.21 Specific Address 2 Bottom [31:0] Register125343.7.22 Specific Address 2 Top [47:32] Register125443.7.23 Specific Address 3 Bottom [31:0] Register125543.7.24 Specific Address 3 Top [47:32] Register125643.7.25 Specific Address 4 Bottom Register[31:0]125743.7.26 Specific Address 4 Top Register[47:32]125843.7.27 Type ID Match 1 Register125943.7.28 Type ID Match 2 Register126043.7.29 Type ID Match 3 Register126143.7.30 Type ID Match 4 Register126243.7.31 IPG Stretch Register126343.7.32 Stacked VLAN Register126443.7.33 Transmit PFC Pause Register126543.7.34 Specific Address 1 Mask Bottom [31:0] Register126643.7.35 Specific Address Mask 1 Top [47:32] Register126743.7.36 Octets Transmitted [31:0] Register126843.7.37 Octets Transmitted [47:32] Register126943.7.38 Frames Transmitted Register127043.7.39 Broadcast Frames Transmitted Register127143.7.40 Multicast Frames Transmitted Register127243.7.41 Pause Frames Transmitted Register127343.7.42 64 Byte Frames Transmitted Register127443.7.43 65 to 127 Byte Frames Transmitted Register127543.7.44 128 to 255 Byte Frames Transmitted Register127643.7.45 256 to 511 Byte Frames Transmitted Register127743.7.46 512 to 1023 Byte Frames Transmitted Register127843.7.47 1024 to 1518 Byte Frames Transmitted Register127943.7.48 Greater Than 1518 Byte Frames Transmitted Register128043.7.49 Transmit Underruns Register128143.7.50 Single Collision Frames Register128243.7.51 Multiple Collision Frames Register128343.7.52 Excessive Collisions Register128443.7.53 Late Collisions Register128543.7.54 Deferred Transmission Frames Register128643.7.55 Carrier Sense Errors Register128743.7.56 Octets Received [31:0] Register128843.7.57 Octets Received [47:32] Register128943.7.58 Frames Received Register129043.7.59 Broadcast Frames Received Register129143.7.60 Multicast Frames Received Register129243.7.61 Pause Frames Received Register129343.7.62 64 Byte Frames Received Register129443.7.63 65 to 127 Byte Frames Received Register129543.7.64 128 to 255 Byte Frames Received Register129643.7.65 256 to 511 Byte Frames Received Register129743.7.66 512 to 1023 Byte Frames Received Register129843.7.67 1024 to 1518 Byte Frames Received Register129943.7.68 1519 to Maximum Byte Frames Received Register130043.7.69 Undersized Frames Received Register130143.7.70 Oversized Frames Received Register130243.7.71 Jabbers Received Register130343.7.72 Frame Check Sequence Errors Register130443.7.73 Length Field Frame Errors Register130543.7.74 Receive Symbol Errors Register130643.7.75 Alignment Errors Register130743.7.76 Receive Resource Errors Register130843.7.77 Receive Overruns Register130943.7.78 IP Header Checksum Errors Register131043.7.79 TCP Checksum Errors Register131143.7.80 UDP Checksum Errors Register131243.7.81 1588 Timer Sync Strobe Seconds [31:0] Register131343.7.82 1588 Timer Sync Strobe Nanoseconds Register131443.7.83 1588 Timer Seconds [31:0] Register131543.7.84 1588 Timer Nanoseconds Register131643.7.85 1588 Timer Adjust Register131743.7.86 1588 Timer Increment Register131843.7.87 PTP Event Frame Transmitted Seconds Register131943.7.88 PTP Event Frame Transmitted Nanoseconds Register132043.7.89 PTP Event Frame Received Seconds Register132143.7.90 PTP Event Frame Received Nanoseconds Register132243.7.91 PTP Peer Event Frame Transmitted Seconds Register132343.7.92 PTP Peer Event Frame Transmitted Nanoseconds Register132443.7.93 PTP Peer Event Frame Received Seconds Register132544. Analog Comparator Controller (ACC)132644.1 Description132644.2 Embedded Characteristics132644.3 Block Diagram132744.4 Pin Name List132844.5 Product Dependencies132844.5.1 I/O Lines132844.5.2 Power Management132844.5.3 Interrupt132844.5.4 Fault Output132844.6 Functional Description132944.6.1 Description132944.6.2 Analog Settings132944.6.3 Output Masking Period132944.6.4 Fault Mode132944.6.5 Register Write Protection132944.7 Analog Comparator Controller (ACC) User Interface133044.7.1 ACC Control Register133144.7.2 ACC Mode Register133244.7.3 ACC Interrupt Enable Register133444.7.4 ACC Interrupt Disable Register133544.7.5 ACC Interrupt Mask Register133644.7.6 ACC Interrupt Status Register133744.7.7 ACC Analog Control Register133844.7.8 ACC Write Protection Mode Register133944.7.9 ACC Write Protection Status Register134045. Analog-Front-End Controller (AFEC)134145.1 Description134145.2 Embedded Characteristics134145.3 Block Diagram134245.4 Signal Description134245.5 Product Dependencies134345.5.1 Power Management134345.5.2 Interrupt Sources134345.5.3 Analog Inputs134345.5.4 Temperature Sensor134345.5.5 I/O Lines134345.5.6 Timer Triggers134445.5.7 PWM Event Line134445.5.8 Fault Output134445.5.9 Conversion Performances134445.6 Functional Description134445.6.1 Analog-Front-End Conversion134445.6.2 Conversion Reference134545.6.3 Conversion Resolution134645.6.3.1 Enhanced Resolution Mode134645.6.4 Conversion Results134645.6.5 Conversion Results Format134945.6.6 Conversion Triggers134945.6.7 Sleep Mode and Conversion Sequencer134945.6.8 Comparison Window135045.6.9 Differential Inputs135045.6.10 Input Gain and Offset135145.6.11 AFEC Timings135245.6.12 Temperature Sensor135345.6.13 Enhanced Resolution Mode and Digital Averaging Function135645.6.14 Automatic Calibration135945.6.15 Buffer Structure136045.6.16 Fault Output136045.6.17 Register Write Protection136045.7 Analog-Front-End Controller (AFEC) User Interface136145.7.1 AFEC Control Register136345.7.2 AFEC Mode Register136445.7.3 AFEC Extended Mode Register136745.7.4 AFEC Channel Sequence 1 Register136945.7.5 AFEC Channel Sequence 2 Register137045.7.6 AFEC Channel Enable Register137145.7.7 AFEC Channel Disable Register137245.7.8 AFEC Channel Status Register137345.7.9 AFEC Last Converted Data Register137445.7.10 AFEC Interrupt Enable Register137545.7.11 AFEC Interrupt Disable Register137645.7.12 AFEC Interrupt Mask Register137745.7.13 AFEC Interrupt Status Register137845.7.14 AFEC Overrun Status Register138045.7.15 AFEC Compare Window Register138145.7.16 AFEC Channel Gain Register138245.7.17 AFEC Channel Calibration DC Offset Register138345.7.18 AFEC Channel Differential Register138445.7.19 AFEC Channel Selection Register138545.7.20 AFEC Channel Data Register138645.7.21 AFEC Channel Offset Compensation Register138745.7.22 AFEC Temperature Sensor Mode Register138845.7.23 AFEC Temperature Compare Window Register138945.7.24 AFEC Analog Control Register139045.7.25 AFEC Write Protection Mode Register139145.7.26 AFEC Write Protection Status Register139246. Digital-to-Analog Converter Controller (DACC)139346.1 Description139346.2 Embedded Characteristics139346.3 Block Diagram139446.4 Signal Description139546.5 Product Dependencies139546.5.1 Power Management139546.5.2 Interrupt Sources139546.5.3 Conversion Performances139546.6 Functional Description139646.6.1 Digital-to-Analog Conversion139646.6.2 Conversion Results139646.6.3 Conversion Triggers139646.6.4 Conversion FIFO139646.6.5 Channel Selection139646.6.6 DACC Timings139746.6.7 Register Write Protection139746.7 Digital-to-Analog Converter Controller (DACC) User Interface139846.7.1 DACC Control Register139946.7.2 DACC Mode Register140046.7.3 DACC Channel Enable Register140446.7.4 DACC Channel Disable Register140546.7.5 DACC Channel Status Register140646.7.6 DACC Conversion Data Register140746.7.7 DACC Interrupt Enable Register140846.7.8 DACC Interrupt Disable Register140946.7.9 DACC Interrupt Mask Register141046.7.10 DACC Interrupt Status Register141146.7.11 DACC Analog Current Register141246.7.12 DACC Write Protection Mode Register141346.7.13 DACC Write Protection Status Register141447. SAM4E Electrical Characteristics141547.1 Absolute Maximum Ratings141547.2 DC Characteristics141647.3 Power Consumption142247.3.1 Backup Mode Current Consumption142247.3.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled142247.3.1.2 Configuration B: 32.768 kHz Crystal Oscillator Enabled142247.3.2 Sleep and Wait Mode Current Consumption142347.3.2.1 Sleep Mode142347.3.2.2 Wait Mode142547.3.3 Active Mode Power Consumption142647.3.3.1 SAM4E Active Power Consumption142747.3.3.2 SAM4E Active Total Power Consumption142847.3.4 Peripheral Power Consumption in Active Mode142947.4 Oscillator Characteristics143047.4.1 32 kHz RC Oscillator Characteristics143047.4.2 4/8/12 MHz RC Oscillators Characteristics143047.4.3 32.768 kHz Crystal Oscillator Characteristics143147.4.4 32.768 kHz Crystal Characteristics143247.4.5 3 to 20 MHz Crystal Oscillator Characteristics143247.4.6 3 to 20 MHz Crystal Characteristics143347.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode143347.4.8 Crystal Oscillator Design Considerations Information143447.4.8.1 Choosing a Crystal143447.4.8.2 Printed Circuit Board (PCB)143447.5 PLLA Characteristics143447.6 USB Transceiver Characteristics143547.6.1 Typical Connection143547.6.2 Electrical Characteristics143547.6.3 Switching Characteristics143647.7 12-bit AFE (Analog Front End) Characteristics143747.7.1 ADC Power Supply143747.7.1.1 ADC Bias Current143747.7.2 External Reference Voltage143847.7.3 ADC Timings143847.7.4 ADC Transfer Function143947.7.4.1 Differential Mode143947.7.4.2 Single-ended Mode143947.7.4.3 Example of LSB Computation144047.7.5 ADC Electrical Characteristics144047.7.5.1 Gain and Offset Errors1440Differential Mode1441Single-ended Mode144247.7.5.2 ADC Electrical Performances1443Single-ended Static Performances1443Single-ended Dynamic Performances1443Differential Static Performances1443Differential Dynamic Performances144310-bit ADC Mode1443Low Voltage Supply144447.7.5.3 ADC Channel Input Impedance1444Track and Hold Time versus Source Output Impedance144547.7.5.4 AFE DAC Offset Compensation144547.7.6 ADC Resolution with Averaging144747.7.6.1 Conditions @ 25°C with Gain =1144747.7.6.2 Conditions @ 25°C with Gain =4144847.8 12-bit DAC Characteristics144947.9 Analog Comparator Characteristics145147.10 Temperature Sensor145147.11 AC Characteristics145247.11.1 Master Clock Characteristics145247.11.2 I/O Characteristics145247.11.3 SPI Characteristics145347.11.3.1 Maximum SPI Frequency145447.11.3.2 SPI Timings145547.11.4 HSMCI Timings145647.11.5 SMC Timings145647.11.5.1 Read Timings145647.11.5.2 Write Timings145847.11.6 USART in SPI Mode Timings146047.11.6.1 USART SPI TImings146247.11.7 Two-wire Serial Interface Characteristics146347.11.8 Ethernet MAC (GMAC) Characteristics146447.11.8.1 Timing Conditions146447.11.8.2 Timing Constraints146447.11.8.3 MII Mode146547.11.9 Embedded Flash Characteristics146748. SAM4E Mechanical Characteristics146948.1 100-ball TFBGA Package Drawing146948.2 144-ball LFBGA Package Drawing147048.3 100-lead LQFP Package Drawing147148.4 144-lead LQFP Package Drawing147248.5 Soldering Profile147348.6 Packaging Resources147349. Marking147450. Ordering Information147551. Errata on SAM4E Devices147651.1 Errata147651.1.1 Watchdog147651.1.1.1 Watchdog Not Stopped in Wait Mode147651.1.2 Brownout Detector147651.1.2.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected147651.1.3 Flash147751.1.3.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State147752. Revision History1478Table of Contents1498サイズ： 6.22MBページ数： 1506Language: Englishマニュアルを開く
