Cypress CY7C68013 マニュアル

目次

• 1. Features (CY7C68013A/14A/15A/16A)

  1
  • 1.1 Features (CY7C68013A/14A only)

    2
  • 1.2 Features (CY7C68015A/16A only)

    2
• 2. Applications

  3
• 3. Functional Overview

  3
  • 3.1 USB Signaling Speed

    3
  • 3.2 8051 Microprocessor

    3
    • 3.2.1 8051 Clock Frequency

      3
    • 3.2.2 USARTS

      3
    • 3.2.3 Special Function Registers

      3
  • 3.3 I2C Bus

    3
  • 3.4 Buses

    3
  • 3.5 USB Boot Methods

    4
  • 3.6 ReNumeration™

    4
  • 3.7 Bus-powered Applications

    4
  • 3.8 Interrupt System

    4
    • 3.8.1 INT2 Interrupt Request and Enable Registers

      4
    • 3.8.2 USB Interrupt Autovectors

      4
    • 3.8.3 FIFO/GPIF Interrupt (INT4)

      5
  • 3.9 Reset and Wakeup

    6
    • 3.9.1 Reset Pin

      6
    • 3.9.2 Wakeup Pins

      7
  • 3.10 Program/Data RAM

    7
    • 3.10.1 Size

      7
    • 3.10.2 Internal Code Memory, EA = 0

      7
    • 3.10.3 External Code Memory, EA = 1

      7
  • 3.11 Register Addresses

    9
  • 3.12 Endpoint RAM

    10
    • 3.12.1 Size

      10
    • 3.12.2 Organization

      10
    • 3.12.3 Setup Data Buffer

      10
    • 3.12.4 Endpoint Configurations (High -speed Mode)

      10
    • 3.12.5 Default Full-Speed Alternate Settings

      11
    • 3.12.6 Default High-Speed Alternate Settings

      11
  • 3.13 External FIFO Interface

    11
    • 3.13.1 Architecture

      11
    • 3.13.2 Master/Slave Control Signals

      11
    • 3.13.3 GPIF and FIFO Clock Rates

      12
  • 3.14 GPIF

    12
    • 3.14.1 Six Control OUT Signals

      12
    • 3.14.2 Six Ready IN Signals

      12
    • 3.14.3 Nine GPIF Address OUT Signals

      12
    • 3.14.4 Long Transfer Mode

      12
  • 3.15 ECC Generation[7]

    12
    • 3.15.1 ECC Implementation

      12
  • 3.16 USB Uploads and Downloads

    12
  • 3.17 Autopointer Access

    12
  • 3.18 I2C Controller

    13
    • 3.18.1 I2C Port Pins

      13
    • 3.18.2 I2C Interface Boot Load Access

      13
    • 3.18.3 I2C Interface General-Purpose Access

      13
  • 3.19 Compatible with Previous Generation EZ-USB FX2

    13
  • 3.20 CY7C68013A/14A and CY7C68015A/16A Differences

    14
• 4. Pin Assignments

  14
  • 4.1 CY7C68013A/15A Pin Descriptions

    21
• 5. Register Summary

  29
• 6. Absolute Maximum Ratings

  36
• 7. Operating Conditions

  36
• 8. Thermal Characteristics

  36
• 9. DC Characteristics

  37
  • 9.1 USB Transceiver

    37
• 10. AC Electrical Characteristics

  37
  • 10.1 USB Transceiver

    37
  • 10.2 Program Memory Read

    38
  • 10.3 Data Memory Read

    39
  • 10.4 Data Memory Write

    40
  • 10.5 PORTC Strobe Feature Timings

    41
  • 10.6 GPIF Synchronous Signals

    42
  • 10.7 Slave FIFO Synchronous Read

    43
  • 10.8 Slave FIFO Asynchronous Read

    44
  • 10.9 Slave FIFO Synchronous Write

    45
  • 10.10 Slave FIFO Asynchronous Write

    46
  • 10.11 Slave FIFO Synchronous Packet End Strobe

    46
  • 10.12 Slave FIFO Asynchronous Packet End Strobe

    47
  • 10.13 Slave FIFO Output Enable

    48
  • 10.14 Slave FIFO Address to Flags/Data

    48
  • 10.15 Slave FIFO Synchronous Address

    49
  • 10.16 Slave FIFO Asynchronous Address

    49
  • 10.17 Sequence Diagram

    50
    • 10.17.1 Single and Burst Synchronous Read Example

      50
    • 10.17.2 Single and Burst Synchronous Write

      51
    • 10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read

      52
    • 10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

      53
• 11. Ordering Information

  54
• 12. Package Diagrams

  55
• 13. PCB Layout Recommendations

  59
• 14. Quad Flat Package No Leads (QFN) Package Design Notes

  60
• Logic Block Diagram

  2
• Logic Block Diagram

  2