データシート目次High-Performance Modified RISC CPU:1DSP Engine Features:1Peripheral Features:1Power Supply PWM Module Features:1Analog Features:2Special Microcontroller Features:2CMOS Technology:2Pin Diagrams3Table of Contents7Most Current Data Sheet8Errata8Customer Notification System81.0 Device Overview9FIGURE 1-1: dsPIC30F1010 Block Diagram10TABLE 1-1: PINOUT I/O Descriptions for dsPIC30F101011FIGURE 1-2: dspic30f2020 block diagram13TABLE 1-2: PINOUT I/O Descriptions for dsPIC30F202014FIGURE 1-3: dsPIC30F2023 Block Diagram16TABLE 1-3: PINOUT I/O Descriptions for dsPIC30F2023172.0 CPU Architecture Overview192.1 Core Overview192.2 Programmer’s Model202.2.1 Software Stack Pointer/ FRAMe pointer202.2.2 Status Register202.2.3 program counter20FIGURE 2-1: Programmer’s Model212.3 Divide Support22TABLE 2-1: Divide Instructions222.4 DSP Engine23TABLE 2-2: DSP Instruction Summary23FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM242.4.1 Multiplier252.4.2 Data Accumulators and Adder/Subtracter252.4.3 Barrel Shifter273.0 Memory Organization293.1 Program Address Space29FIGURE 3-1: program Space memory map FOR dsPIC30F1010/202X29TABLE 3-1: Program Space Address Construction30FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION303.1.1 Data Access From Program Memory using Table Instructions31FIGURE 3-3: Program Data Table Access (Least Significant Word)31FIGURE 3-4: Program Data Table Access (Most Significant Byte)323.1.2 Data Access from Program Memory Using Program Space Visibility32FIGURE 3-5: Data Space Window Into Program Space Operation333.2 Data Address Space333.2.1 Data Space Memory Map33FIGURE 3-6: DATA SPACE MEMORY MAP34FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS353.2.2 Data Spaces36TABLE 3-2: Effect of Invalid Memory Accesses363.2.3 Data Space Width363.2.4 Data Alignment36FIGURE 3-8: DATA ALIGNMENT363.2.5 Near Data Space373.2.6 Software Stack37FIGURE 3-9: CALL Stack FRAME373.2.7 Data RAM Protection37TABLE 3-3: Core Register Map384.0 Address Generator Units414.1 Instruction Addressing Modes414.1.1 file register instructions41TABLE 4-1: Fundamental Addressing Modes Supported414.1.2 mcu instructions424.1.3 Move and accumulator instructions424.1.4 Mac instructions424.1.5 other instructions424.2 Modulo Addressing434.2.1 Start and End Address434.2.2 W Address Register Selection43FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE444.2.3 Modulo Addressing Applicability454.3 Bit-Reversed Addressing454.3.1 Bit-Reversed Addressing Implementation45FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE45TABLE 4-2: BiT-Reversed Address Sequence (16-entry)46TABLE 4-3: Bit-Reversed Address Modifier Values For XBREV Register465.0 Interrupts475.1 Interrupt Priority48TABLE 5-1: dsPIC30F1010/202X Interrupt Vector Table485.2 Reset Sequence495.2.1 Reset Sources495.3 Traps495.3.1 Trap Sources495.3.2 Hard and Soft Traps50FIGURE 5-1: Trap Vectors505.4 Interrupt Sequence51FIGURE 5-2: INTERRUPT STACK FRAME515.5 Alternate Vector Table515.6 Fast Context Saving515.7 External Interrupt Requests515.8 Wake-up from Sleep and Idle51Register 5-1: IntCON1: Interrupt Control Register 152Register 5-2: INTCON2: Interrupt Control REgister 254Register 5-3: IFs0: Interrupt Flag Status Register 055Register 5-4: IFS1: Interrupt Flag STatus Register 157Register 5-5: IFS2: Interrupt Flag Status Register 258Register 5-6: IEC0: Interrupt Enable Control Register 059Register 5-7: IEC1: Interrupt Enable Control Register 161Register 5-8: IEC2: Interrupt Enable Control Register 262Register 5-9: IPC0: Interrupt Priority Control Register 063Register 5-10: IPC1: Interrupt Priority Control Register 164Register 5-11: IPC2: Interrupt Priority Control Register 265Register 5-12: IPC3: Interrupt Priority Control Register 366Register 5-13: IPC4: Interrupt Priority Control Register 467Register 5-14: IPC5: Interrupt Priority Control Register 568Register 5-15: IPC6: Interrupt Priority Control Register 669Register 5-16: IPC7: Interrupt Priority Control Register 770Register 5-17: IPC8: Interrupt Priority Control Register 871Register 5-18: IPC9: Interrupt Priority Control Register 972Register 5-19: IPC10: Interrupt Priority Control Register 1073Register 5-20: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER74TABLE 5-2: Interrupt Controller Register Map756.0 I/O Ports776.1 Parallel I/O (PIO) Ports77FIGURE 6-1: Block Diagram of a ShAred PORT Structure776.2 Configuring Analog Port Pins786.2.1 I/O Port Write/Read Timing78EXAMPLE 6-1: Port Write/Read Example786.3 Input Change Notification78TABLE 6-1: dsPIC30F1010/2020 Port Register Map79TABLE 6-2: dsPIC30F2023 Port Register MAp80TABLE 6-3: dsPIC30F1010/202x INPUT CHANGE NOTIFICATION REGISTER MAP807.0 Flash Program Memory817.1 In-Circuit Serial Programming (ICSP)817.2 Run-Time Self-Programming (RTSP)817.3 Table Instruction Operation Summary81FIGURE 7-1: ADDRESSING FOR TABLE AND NVM REGISTERS817.4 RTSP Operation827.5 Control Registers827.5.1 NVMCON Register827.5.2 NVMADR Register827.5.3 NVMADRU Register827.5.4 NVMKEY Register827.6 Programming Operations837.6.1 Programming Algorithm for Program Flash837.6.2 Erasing a Row of Program Memory83EXAMPLE 7-1: erasing A row of PROGRAM memory837.6.3 Loading Write Latches84EXAMPLE 7-2: loading write latches847.6.4 Initiating The Programming Sequence84EXAMPLE 7-3: initiating a programming sequence84TABLE 7-1: NVM Register Map858.0 Timer1 Module87FIGURE 8-1: 16-bit Timer1 Module Block diagram (Type A Timer)888.1 Timer Gate Operation888.2 Timer Prescaler888.3 Timer Operation During Sleep Mode888.4 Timer Interrupt88TABLE 8-1: Timer1 Register Map899.0 Timer2/3 Module91FIGURE 9-1: 32-bit TIMER2/3 BLOCK DIAGRAM92FIGURE 9-2: 16-bit TIMER2 BLOCK DIAGRAM93FIGURE 9-3: 16-bit TIMER3 BLOCK DIAGRAM939.1 Timer Gate Operation949.2 ADC Event Trigger949.3 Timer Prescaler949.4 Timer Operation During Sleep Mode949.5 Timer Interrupt94TABLE 9-1: Timer2/3 register map9510.0 Input Capture Module97FIGURE 10-1: Input Capture Mode Block Diagram9710.1 Simple Capture Event Mode9810.1.1 Capture Prescaler9810.1.2 Capture Buffer Operation9810.1.3 Timer2 and Timer3 selection mode9810.1.4 Hall Sensor Mode9810.2 Input Capture Operation During Sleep and Idle Modes9910.2.1 Input Capture in CPU Sleep Mode9910.2.2 Input Capture in CPU Idle Mode9910.3 Input Capture Interrupts99TABLE 10-1: Input Capture Register Map10011.0 Output Compare Module101FIGURE 11-1: Output Compare Mode Block Diagram10111.1 Timer2 and Timer3 Selection Mode10211.2 Simple Output Compare Match Mode10211.3 Dual Output Compare Match Mode10211.3.1 Single Pulse Mode10211.3.2 Continuous Pulse Mode10211.4 Simple PWM Mode10211.4.1 PWM Period103EQUATION 11-1: PWM Period10311.4.2 PWM with FAULt protection Input pin10311.5 Output Compare Operation During CPU Sleep Mode10311.6 Output Compare Operation During CPU Idle Mode103FIGURE 11-1: PWM output Timing10411.7 Output Compare Interrupts104TABLE 11-1: Output Compare Register Map10512.0 Power Supply PWM10712.1 Features Overview10712.2 Description107FIGURE 12-1: Simplified Conceptual Block Diagram of Power Supply PWM108FIGURE 12-2: Partitioned output Pair, complementary PWM Mode10912.3 Control Registers109Register 12-1: PTCON: PWM Time Base Control Register110Register 12-2: PTPER: Primary Time Base Register111Register 12-3: SEVTCMP: PWM Special Event Compare Register111Register 12-4: MDC: PWM Master Duty Cycle Register112Register 12-5: PWMCONx: PWM Control Register112Register 12-6: PDCx: PWM Generator Duty Cycle Register113Register 12-7: PHASEx: PWM Phase-Shift Register114Register 12-8: DTRx: PWM Dead-Time Register114Register 12-9: ALTDTRx: PWM Alternate Dead-Time Register115Register 12-10: TRGCONx: PWM TRIGGER Control Register115Register 12-11: IOCONx: PWM I/O Control Register116Register 12-12: FCLCONx: PWM Fault Current-Limit Control Register117Register 12-13: TRIGx: PWM Trigger Compare Value Register119Register 12-14: LEBCONx: Leading Edge Blanking Control Register12012.4 Module Functionality12112.4.1 Standard Edge-Aligned PWM Mode121FIGURE 12-3: Edge-Aligned PWM12112.4.2 Complementary PWM Mode121FIGURE 12-4: Complementary PWM12112.4.3 Push-Pull PWM Mode121FIGURE 12-5: Push-Pull PWM12112.4.4 Multi-Phase PWM Mode122FIGURE 12-6: Multi-Phase PWM12212.4.5 Variable Phase PWM Mode122FIGURE 12-7: Variable Phase PWM12212.4.6 Current-Limit PWM Mode122FIGURE 12-8: Cycle-by-Cycle Current-LIMIT PWM Mode12212.4.7 Constant Off-Time PWM123FIGURE 12-9: Constant Off-Time PWM12312.4.8 Current Reset PWM Mode123FIGURE 12-10: Current Reset PWM12312.4.9 Independent Time Base PWM123FIGURE 12-11: Independent Time base PWM12312.5 Primary PWM Time Base124FIGURE 12-12: PTMR Block Diagram12412.5.1 PTMR Synchronization12412.6 Primary PWM Time Base Roll Counter12412.7 Individual PWM Time Base(s)124FIGURE 12-13: TMRx Block Diagram12512.8 PWM Period12512.9 PWM Frequency and Duty Cycle Resolution125TABLE 12-1: Available Pwm frequencies and resolutions @ 30 MIPS125TABLE 12-2: Available Pwm frequencies and resolutions @ 20 MIPS12512.10 PWM Duty Cycle Comparison Units126FIGURE 12-14: Duty Cycle Comparison12612.11 Complementary PWM Outputs12612.12 Independent PWM Outputs12612.13 Duty Cycle Limits12612.14 Dead-Time Generation127FIGURE 12-15: Dead-Time Insertion for Complementary PWM127FIGURE 12-16: Dead-time Control Units block diagram12712.14.1 DEAD-TIME GENERATORS12712.14.2 Alternate Dead-Time Source127FIGURE 12-17: DUal dead-time waveforms12812.14.3 Dead-Time ranges128TABLE 12-3: Example Dead-Time Ranges12812.14.4 Dead-Time Insertion Timing12812.14.5 Dead-Time distortion128FIGURE 12-18: Dead-Time insertion (PWM OUTPUT SIGNAL TIMING MAY BE DELAYED)12812.15 Configuring a PWM Channel12912.16 Speed Limits of PWM Output Circuitry12912.17 PWM Special Event Trigger12912.17.1 Special Event Trigger Enable12912.17.2 Special Event Trigger postscaler12912.18 Individual PWM Triggers129EXAMPLE 12-1: Code Example for Configuring PWM Channel 1130FIGURE 12-19: PWM Trigger Block Diagram13112.19 PWM Interrupts13112.20 PWM Time Base Interrupts13112.21 PWM Fault and Current-Limit Pins13112.22 Leading Edge Blanking13112.23 PWM Fault Pins132FIGURE 12-20: PWM Fault Control Logic Diagram13212.23.1 Fault Interrupts13312.23.2 Fault states13312.23.3 Fault input modes13312.23.4 Fault ENTRY13312.23.5 Fault EXIT13312.23.6 Fault exit with PTMR disabled13312.23.7 Fault Pin Software Control13312.24 PWM Current-Limit Pins13412.24.1 Current-Limit Interrupts134FIGURE 12-21: PWM Current-Limit Control Logic Diagram13412.25 Simultaneous PWM Faults and Current Limits13512.26 PWM Fault and Current-Limit TRG Outputs To ADC13512.27 PWM Output Override Priority13512.28 Fault and Current-Limit Override Issues with Dead-Time Logic13512.29 Asserting Outputs via Current Limit13512.30 PWM Immediate Update13512.31 PWM Output Override13512.31.1 complementary output mode13512.31.2 override synchronization13612.32 Functional Exceptions13612.32.1 Power Reset Conditions13612.32.2 SLEEP Mode13612.32.3 CPU IDLE Mode13612.33 Register Bit Alignment13612.34 Application Examples:13712.34.1 Standard PWM Mode137FIGURE 12-22: Applications of Standard PWM Mode13712.34.2 Application of Complementary PWM Mode137FIGURE 12-23: Applications of Complementary PWM mode13712.34.3 Application of Push-Pull PWM Mode138FIGURE 12-24: Applications of Push- Pull Pwm Mode13812.34.4 Application of Multi-Phase PWM Mode138FIGURE 12-25: Applications of Multi- Phase Pwm Mode13812.34.5 Application of Variable Phase PWM Mode139FIGURE 12-26: Application of Variable Phase PWM mode13912.34.6 Application of Current Reset PWM Mode139FIGURE 12-27: Application of Current Reset PWM mode13912.35 Methods to reduce EMI14012.35.1 Method #1: programmable FRC dither14012.35.2 Method #2: Software Controlled Dither14012.35.3 Method #3: Software Scaling of Time Base Period14012.35.4 Method #4: Frequency Modulation14012.35.5 INDEPENDENT PWM CHANNEL DITHERING ISSUES:14012.36 External Synchronization Features14112.37 CPU Load Staggering14112.38 External Trigger Blanking141TABLE 12-4: Power Supply PWM Register Map14213.0 Serial Peripheral Interface (SPI)145FIGURE 13-1: SPI Module Block Diagram146FIGURE 13-2: SPI Master/Slave Connection147FIGURE 13-3: SPI Master, Frame Master Connection Diagram147FIGURE 13-4: SPI Master, Frame Slave Connection Diagram147FIGURE 13-5: SPI Slave, Frame Master Connection Diagram148FIGURE 13-6: SPI Slave, Frame Slave Connection Diagram148EQUATION 13-1: Relationship Between Device and SPI Clock Speed148TABLE 13-1: Sample SCKx Frequencies148Register 13-1: SPIxSTAT: SPIx Status and Control Register149Register 13-2: SPIxCON1: SPIx Control Register 1150Register 13-3: SPIxCON2: SPIx Control Register 2151TABLE 13-2: SPI1 Register Map15214.0 I2C™ Module15314.1 Operating Function Description15314.1.1 VARIOUS I2C MODES15314.1.2 Pin Configuration In I2C Mode153FIGURE 14-1: Programmer’s model15314.1.3 I2C Registers153FIGURE 14-2: I2C™ BLOCK DIAGRAM15414.2 I2C Module Addresses15514.3 I2C 7-bit Slave Mode Operation15514.3.1 Slave Transmission15514.3.2 Slave Reception15514.4 I2C 10-bit Slave Mode Operation15514.4.1 10-bit Mode Slave Transmission15514.4.2 10-bit Mode Slave Reception15514.5 Automatic Clock Stretch15614.5.1 transmit Clock Stretching15614.5.2 RECEIVE CLOCK STRETCHING15614.5.3 Clock Stretching During 7-bit Addressing (STREN = 1)15614.5.4 Clock Stretching During 10-bit Addressing (STREN = 1)15614.6 Software Controlled Clock Stretching (STREN = 1)15614.7 Interrupts15614.8 Slope Control15714.9 IPMI Support15714.10 General Call Address Support15714.11 I2C Master Support15714.12 I2C Master Operation15714.12.1 I2C Master Transmission15714.12.2 I2C Master Reception15714.12.3 Baud Rate Generator15814.12.4 Clock Arbitration15814.12.5 Multi-Master Communication, Bus Collision And Bus Arbitration15814.13 I2C Module Operation During CPU Sleep and Idle Modes15814.13.1 I2C Operation During CPU Sleep MoDE15814.13.2 I2C Operation During CPU Idle Mode158TABLE 14-1: I2C™ Register Map15915.0 Universal Asynchronous Receiver Transmitter (UART) Module161FIGURE 15-1: UART Simplified Block Diagram16115.1 UART Baud Rate Generator (BRG)162EQUATION 15-1: UART Baud Rate with BRGH = 0(1,2,3)162EQUATION 15-2: UART Baud Rate with BRGH = 1(1,2,3)162EXAMPLE 15-1: Baud Rate Error Calculation (BRGH = 0)(1)16215.2 Transmitting in 8-bit Data Mode16315.3 Transmitting in 9-bit Data Mode16315.4 Break and Sync Transmit Sequence16315.5 Receiving in 8-bit or 9-bit Data Mode16315.6 Built-in IrDA Encoder and Decoder16315.7 Alternate UART I/O Pins163Register 15-1: U1MODE: UART1 MODE Register164Register 15-2: U1STA: UART1 Status and Control Register166TABLE 15-1: UART1 Register Map16816.0 10-bit 2 Msps Analog-to- Digital Converter (ADC) Module16916.1 Features16916.2 Description16916.3 Module Functionality169FIGURE 16-1: ADC Block Diagram170Register 16-1: A/D Control Register (ADCON)171Register 16-2: A/D Status Register (ADSTAT)173Register 16-3: A/D Base Register (ADBASE)174Register 16-4: A/D Port Configuration Register (ADPCFG)174Register 16-5: A/D Convert Pair Control Register 0 (ADCPC0)175Register 16-6: A/D Convert Pair Control Register 1 (ADCPC1)177Register 16-7: A/D Convert Pair Control Register 2 (ADCPC2)17916.4 ADC Result Buffer18116.5 Application Information181FIGURE 16-2: Application Example: Importance of Precise Sampling18116.6 Reverse Conversion Order18216.7 Simultaneous and Sequential Sampling in a pair18216.8 Group Interrupt Generation18216.9 Individual Pair Interrupts18316.10 Early Interrupt Generation18316.11 Conflict Resolution18316.12 Deliberate Conflicts18316.13 ADC Clock Selection18316.14 ADC Base Register183EXAMPLE 16-1: ADC Base Register Code184EXAMPLE 16-1: ADC Base Register Code (Continued)18516.15 Changing A/D Clock18516.16 Sample and Conversion18516.17 A/D Sample and Convert Timing186FIGURE 16-3: Detailed Conversion sequence timings, SEQSAMP = 0, not busy186FIGURE 16-4: Detailed Conversion sequence timings, SEQSAMP = 118716.18 Module Power-Down Modes18816.19 Effects of a Reset18816.20 Configuring Analog Port Pins18816.21 Output Formats188FIGURE 16-5: A/D Output Data Format189TABLE 16-1: ADC Register Map19017.0 SMPS Comparator Module19117.1 Features Overview191FIGURE 17-1: Comparator Module Block Diagram19117.2 Module Applications19117.3 Module Description19217.4 DAC19217.5 Interaction with I/O Buffers19217.6 Digital Logic19217.7 Comparator Input Range19217.8 DAC Output Range19217.9 Comparator Registers192Register 17-1: Comparator Control Registerx (CMPCONx)193Register 17-2: Comparator DAC Control Registerx (CMPDACx)194TABLE 17-1: Analog ComparAtor Control Register Map19518.0 System Integration19718.1 Oscillator System Overview19718.2 Oscillator Control Registers197FIGURE 18-1: OSCILLATOR SYSTEM BLOCK DIAGRAM198Register 18-1: OSCCON: Oscillator Control Register199Register 18-2: OSCTUN: Oscillator TUNING Register201Register 18-3: OSCTUN2: Oscillator Tuning Register 2202Register 18-4: LFSR: Linear Feedback Shift Register202Register 18-5: FOSCSEL: Oscillator Selection Configuration Bits203Register 18-6: FOSC: Oscillator Selection Configuration Bits20418.2.1 accidental write Protection20518.3 Oscillator Configurations205FIGURE 18-2: System Clock and Fadc Derivation20518.3.1 Initial Clock source selection206TABLE 18-1: Configuration Bit Values for Clock Selection20618.3.2 Oscillator Start-up Timer (OST)20618.3.3 Phase Locked Loop (PLL)206TABLE 18-2: PLL frequency range20618.4 PRIMARY oscillator on OSC1/ OSC2 pins:207FIGURE 18-3: Primary oscillator20718.5 External Clock Input207FIGURE 18-4: External Clock Input Operation (EC oscillator Configuration)207FIGURE 18-5: External Clock Input Operation (ECIO oscillator Configuration)20718.6 Internal Fast RC oscillator (FRC)20818.6.1 Frequency Range Selection20818.6.2 Nominal Frequency Values20818.6.3 FRC Frequency USER TUNING20818.6.4 Clock dithering logic20818.6.5 frequency sequencing mode20818.6.6 Pseudo random clock dithering mode20818.6.7 Fail-Safe Clock Monitor20818.7 Reset209FIGURE 18-6: FRC TUNE Dither Logic Block Diagram210FIGURE 18-7: Reset SYSTEM BLOCK DIAGRAM21018.7.1 POR: Power-ON reset211FIGURE 18-8: Time-out Sequence on Power-up (MCLR Tied to Vdd)211FIGURE 18-9: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1211FIGURE 18-10: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2212FIGURE 18-11: External Power-on Reset Circuit (for Slow Vdd Power-up)212TABLE 18-3: Initialization Condition for RCON RegisteR CASE 1213TABLE 18-4: Initialization Condition for RCON RegisteR CASE 221318.8 Watchdog Timer (WDT)21418.8.1 Watchdog Timer Operation21418.8.2 Enabling and Disabling the WDT21418.9 Power-Saving Modes21418.9.1 Sleep Mode21418.9.2 Idle Mode21518.10 Device Configuration Registers215TABLE 18-5: FGS and FBS Bit descriptions for the dsPIC30F1010216TABLE 18-6: FGS and FBS Bit Descriptions for the dsPIC30F202x216TABLE 18-7: FWDT and FPOR bit descriptions for dsPIC30F1010/202X21718.11 In-Circuit Debugger217TABLE 18-8: System Integration Register Map For dsPIC30F202x218TABLE 18-9: DEVICE Configuration Register Map21819.0 Instruction Set Summary219TABLE 19-1: Symbols used in Opcode Descriptions220TABLE 19-2: Instruction Set OVERVIEW22220.0 Development Support22720.1 MPLAB X Integrated Development Environment Software22720.2 MPLAB XC Compilers22820.3 MPASM Assembler22820.4 MPLINK Object Linker/ MPLIB Object Librarian22820.5 MPLAB Assembler, Linker and Librarian for Various Device Families22820.6 MPLAB X SIM Software Simulator22920.7 MPLAB REAL ICE In-Circuit Emulator System22920.8 MPLAB ICD 3 In-Circuit Debugger System22920.9 PICkit 3 In-Circuit Debugger/ Programmer22920.10 MPLAB PM3 Device Programmer22920.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits23020.12 Third-Party Development Tools23021.0 Electrical Characteristics231Absolute Maximum Ratings(†)23121.1 DC Characteristics231TABLE 21-1: Operating MIPS vs. Voltage231TABLE 21-2: Thermal Operating Conditions232TABLE 21-3: Thermal Packaging Characteristics232TABLE 21-4: DC Temperature and Voltage specifications232TABLE 21-5: DC Characteristics: Operating Current (Idd)233TABLE 21-6: DC Characteristics: Idle Current (iidle)235TABLE 21-7: DC Characteristics: Power-Down Current (Ipd)237TABLE 21-8: DC Characteristics: I/O Pin Input Specifications238TABLE 21-9: DC Characteristics: I/O Pin Output Specifications239TABLE 21-10: DC Characteristics: Program and EEPROM23921.2 AC Characteristics and Timing Parameters240TABLE 21-11: Temperature and Voltage Specifications – AC240FIGURE 21-1: Load Conditions for Device Timing Specifications240FIGURE 21-2: External Clock Timing240TABLE 21-12: External Clock Timing Requirements241TABLE 21-13: PLL Clock Timing Specifications (Vdd = 3.0 AND 5.0V )242TABLE 21-14: Internal Clock Timing examples242TABLE 21-15: AC Characteristics: Internal RC Accuracy243TABLE 21-16: AC Characteristics: Internal RC Jitter244FIGURE 21-3: CLKO and I/O Timing Characteristics245TABLE 21-17: CLKO and I/O Timing Requirements245FIGURE 21-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics246TABLE 21-18: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Timing Requirements247FIGURE 21-5: band gap Start-up Time Characteristics248TABLE 21-19: band gap Start-up Time Requirements248FIGURE 21-6: Timerx External Clock Timing Characteristics249TABLE 21-20: Timer1 External Clock Timing Requirements249TABLE 21-21: Timer2 External Clock Timing Requirements250TABLE 21-22: Timer3 External Clock Timing Requirements250FIGURE 21-7: INPUT CAPTURE x (ICx) TIMING Characteristics251TABLE 21-23: Input Capture x timing requirements251FIGURE 21-8: Output Compare x (OCx) Module Timing Characteristics251TABLE 21-24: Output Compare x Module timing requirements251FIGURE 21-9: OCx/PWM Module Timing Characteristics252TABLE 21-25: Simple OCx/PWM MODE Timing Requirements252FIGURE 21-10: Power Supply PWM Module fault Timing Characteristics253FIGURE 21-11: Power Supply PWM Module Timing Characteristics253TABLE 21-26: Power Supply PWM Module Timing Requirements253FIGURE 21-12: SPIx Module Master Mode (CKE = 0) Timing Characteristics254TABLE 21-27: SPIx Master mode (cke = 0) Timing requirements254FIGURE 21-13: SPIx Module Master Mode (CKE = 1) Timing Characteristics255TABLE 21-28: SPIx Module Master mode (cke = 1) Timing requirements255FIGURE 21-14: SPIx Module Slave Mode (CKE = 0) Timing Characteristics256TABLE 21-29: SPIx Module Slave mode (cke = 0) Timing requirements256FIGURE 21-15: SPIx Module Slave Mode (CKE = 1) Timing Characteristics257TABLE 21-30: SPIx Module Slave mode (cke = 1) Timing requirements258FIGURE 21-16: I2C™ Bus Start/Stop Bits Timing Characteristics (Master mode)259FIGURE 21-17: I2C™ Bus Data Timing Characteristics (Master mode)259TABLE 21-31: I2C™ Bus Data Timing Requirements (Master Mode)260FIGURE 21-18: I2C™ Bus Start/Stop Bits Timing Characteristics (slave mode)261FIGURE 21-19: I2C™ Bus Data Timing Characteristics (slave mode)261TABLE 21-32: I2C™ Bus Data Timing Requirements (Slave Mode)262TABLE 21-33: 10-bit High-speed a/d Module Specifications263FIGURE 21-20: A/d Conversion Timing Per Input264TABLE 21-34: Comparator Operating Conditions265TABLE 21-35: comparator AC AND DC Specifications265TABLE 21-36: DAC DC Specifications265TABLE 21-37: DAC AC Specifications26522.0 Package Marking Information26728-Lead Plastic Quad Flat, No Lead Package (MM) - 6x6x0.9 mm Body (QFN-S) With 0.40 mm Contact Length26828-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)26928-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)27044-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)27144-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body (QFN)272The Microchip Web Site273Customer Change Notification Service273Customer Support273Appendix A: Revision History275Revision A (June 2006)275Revision B (August 2006)275Revision C (November 2006)275Revision D (March 2014)275INDEX277Product Identification System283Worldwide Sales and Service286サイズ: 1.93MBページ数: 286Language: Englishマニュアルを開く