データシート目次High-Performance RISC CPU:3Special Microcontroller Features:3PIC16LF1946/47 Low-Power Features:3Peripheral Features:3Peripheral Features (Continued):4Pin Diagram – 64-Pin TQFP/QFN (PIC16(L)F1946/47)5Table of Contents8Most Current Data Sheet9Errata9Customer Notification System91.0 Device Overview11TABLE 1-1: Device Peripheral Summary11FIGURE 1-1: PIC16(L)F1946/47 Block Diagram12TABLE 1-2: PIC16(L)F1946/47 Pinout Description132.0 Enhanced Mid-Range CPU192.1 Automatic Interrupt Context Saving192.2 16-level Stack with Overflow and Underflow192.3 File Select Registers192.4 Instruction Set19FIGURE 2-1: Core Block Diagram203.0 Memory Organization213.1 Program Memory Organization21TABLE 3-1: Device Sizes and Addresses21FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F194622FIGURE 3-2: Program Memory Map And Stack For PIC16(L)F1947223.1.1 Reading Program Memory as Data23EXAMPLE 3-1: RETLW Instruction23EXAMPLE 3-2: Accessing Program Memory Via FSR243.2 Data Memory Organization243.2.1 Core Registers24TABLE 3-2: Core Registers243.3 Register Definitions: Status25Register 3-1: STATUS: STATUS Register253.3.1 Special Function Register263.3.2 General Purpose RAM263.3.3 Common RAM26FIGURE 3-3: Banked Memory Partitioning263.3.4 Device Memory Maps26TABLE 3-3: Memory Map Tables26TABLE 3-4: PIC16(L)F1946/47 Memory Map, Banks 0-727TABLE 3-5: PIC16(L)F1946/47 Memory Map, Banks 8-1528TABLE 3-6: PIC16(L)F1946/47 Memory Map, Banks 16-2329TABLE 3-7: PIC16(L)F1946/47 Memory Map, Banks 24-3130TABLE 3-8: PIC16(L)F1946/47 Memory Map, Bank 1531TABLE 3-9: PIC16(L)F1946/47 Memory Map, Bank 31313.3.5 Special Function Registers Summary32TABLE 3-10: Special Function Register Summary333.4 PCL and PCLATH48FIGURE 3-4: Loading Of PC In Different Situations483.4.1 Modifying PCL483.4.2 computed goto483.4.3 Computed Function Calls483.4.4 Branching483.5 Stack493.5.1 Accessing the Stack49FIGURE 3-5: Accessing the Stack Example 149FIGURE 3-6: Accessing the Stack Example 250FIGURE 3-7: Accessing the Stack Example 350FIGURE 3-8: Accessing the Stack Example 4513.5.2 Overflow/Underflow Reset513.6 Indirect Addressing51FIGURE 3-9: Indirect Addressing523.6.1 Traditional Data Memory53FIGURE 3-10: Traditional Data Memory Map533.6.2 Linear Data Memory54FIGURE 3-11: Linear Data Memory Map543.6.3 Program Flash Memory54FIGURE 3-12: Program Flash Memory Map544.0 Device Configuration554.1 Configuration Words554.2 Register Definitions: Configuration Words56Register 4-1: CONFIG1: Configuration Word 156Register 4-2: CONFIG2: Configuration Word 2584.3 Code Protection594.3.1 Program Memory Protection594.3.2 Data EEPROM Protection594.4 Write Protection594.5 User ID594.6 Device ID and Revision ID604.7 Register Definitions: Device ID60Register 4-3: DEVICEID: Device ID Register605.0 Oscillator Module (With Fail-Safe Clock Monitor)615.1 Overview61FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram625.2 Clock Source Types635.2.1 External Clock Sources63FIGURE 5-2: External Clock (EC) Mode Operation63FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)64FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)64FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)65FIGURE 5-6: External RC Modes655.2.2 Internal Clock Sources66FIGURE 5-7: Internal Oscillator Switch Timing695.3 Clock Switching705.3.1 System Clock Select (SCS) Bits705.3.2 Oscillator Start-up Time-out Status (OSTS) Bit705.3.3 Timer1 Oscillator705.3.4 Timer1 Oscillator Ready (T1OSCR) Bit705.4 Two-Speed Clock Start-up Mode715.4.1 Two-Speed Start-up Mode Configuration71TABLE 5-1: Oscillator Switching Delays715.4.2 Two-speed Start-up Sequence725.4.3 Checking Two-Speed Clock Status72FIGURE 5-8: Two-Speed Start-up725.5 Fail-Safe Clock Monitor73FIGURE 5-9: FSCM Block Diagram735.5.1 Fail-Safe Detection735.5.2 Fail-Safe Operation735.5.3 Fail-Safe Condition Clearing735.5.4 Reset or Wake-up from Sleep73FIGURE 5-10: FSCM Timing Diagram745.6 Register Definitions: Oscillator Control75Register 5-1: OSCCON: Oscillator Control Register75Register 5-2: OSCSTAT: Oscillator Status Register76Register 5-3: OSCTUNE: Oscillator Tuning Register77TABLE 5-2: Summary of Registers Associated with Clock Sources77TABLE 5-3: Summary of Configuration Word with Clock Sources776.0 Resets79FIGURE 6-1: Simplified Block Diagram Of On-Chip Reset Circuit796.1 Power-on Reset (POR)806.1.1 Power-up Timer (PWRT)806.2 Brown-Out Reset (BOR)80TABLE 6-1: BOR Operating Modes806.2.1 BOR is Always On806.2.2 BOR is Off in Sleep806.2.3 BOR Controlled by Software80FIGURE 6-2: Brown-Out Situations816.3 Register Definitions: BOR Control81Register 6-1: BORCON: Brown-out Reset Control Register816.4 MCLR82TABLE 6-2: MCLR Configuration826.4.1 MCLR Enabled826.4.2 MCLR Disabled826.5 Watchdog Timer (WDT) Reset826.6 RESET Instruction826.7 Stack Overflow/Underflow Reset826.8 Programming Mode Exit826.9 Power-Up Timer826.10 Start-up Sequence82FIGURE 6-3: Reset Start-Up Sequence836.11 Determining the Cause of a Reset84TABLE 6-3: Reset Status Bits and Their Significance84TABLE 6-4: Reset Condition for Special Registers(2)846.12 Power Control (PCON) Register856.13 Register Definitions: Power Control85Register 6-2: PCON: Power Control Register85TABLE 6-5: Summary Of Registers Associated With Resets867.0 Interrupts87FIGURE 7-1: Interrupt Logic877.1 Operation887.2 Interrupt Latency88FIGURE 7-2: Interrupt Latency89FIGURE 7-3: INT Pin Interrupt Timing907.3 Interrupts During Sleep917.4 INT Pin917.5 Automatic Context Saving917.6 Register Definitions: Interrupt Control92Register 7-1: INTCON: Interrupt Control Register92Register 7-2: PIE1: Peripheral Interrupt Enable Register 193Register 7-3: PIE2: Peripheral Interrupt Enable Register 294Register 7-4: PIE3: Peripheral Interrupt Enable Register 395Register 7-5: PIE4: Peripheral Interrupt Enable Register 496Register 7-6: PIR1: Peripheral Interrupt Request Register 197Register 7-7: PIR2: Peripheral Interrupt Request Register 298Register 7-8: PIR3: Peripheral Interrupt Request Register 399Register 7-9: PIR4: Peripheral Interrupt Request Register 4100TABLE 7-1: Summary of Registers Associated with Interrupts1018.0 Low Dropout (LDO) Voltage Regulator103TABLE 8-1: VCAPEN Select Bit103TABLE 8-2: Summary of Configuration Word with LDO1039.0 Power-Down Mode (Sleep)1059.1 Wake-up from Sleep1059.1.1 Wake-up Using Interrupts106FIGURE 9-1: Wake-Up From Sleep Through Interrupt106TABLE 9-1: Summary of Registers Associated with Power-Down Mode10610.0 Watchdog Timer (WDT)107FIGURE 10-1: Watchdog Timer Block Diagram10710.1 Independent Clock Source10810.2 WDT Operating Modes10810.2.1 WDT Is Always On10810.2.2 WDT Is Off In Sleep10810.2.3 WDT Controlled By Software108TABLE 10-1: WDT Operating Modes10810.3 Time-Out Period10810.4 Clearing the WDT10810.5 Operation During Sleep108TABLE 10-2: WDT Clearing Conditions10810.6 Register Definitions: Watchdog Control109Register 10-1: WDTCON: Watchdog Timer Control Register109TABLE 10-3: Summary of Registers Associated with Watchdog Timer110TABLE 10-4: Summary of Configuration Word with Watchdog Timer11011.0 Data EEPROM and Flash Program Memory Control11111.1 EEADRL and EEADRH Registers11111.1.1 EECON1 and EECON2 Registers11111.2 Using the Data EEPROM11211.2.1 Reading the Data EEPROM Memory112EXAMPLE 11-1: Data EEPROM Read11211.2.2 Writing to the Data EEPROM Memory11211.2.3 Protection Against Spurious Write11211.2.4 Data EEPROM Operation During Code-Protect112EXAMPLE 11-2: Data EEPROM Write113FIGURE 11-1: Flash Program Memory Read Cycle Execution11311.3 Flash Program Memory Overview11411.3.1 Reading the Flash Program Memory114TABLE 11-1: Flash Memory Organization By Device114EXAMPLE 11-3: Flash Program Memory Read11511.3.2 Erasing Flash Program Memory11611.3.3 Writing to Flash Program Memory116FIGURE 11-2: Block Writes to Flash Program Memory With 32 write latches117EXAMPLE 11-4: Erasing One Row of Program Memory -118EXAMPLE 11-5: Writing to Flash Program Memory11911.4 Modifying Flash Program Memory12011.5 User ID, Device ID and Configuration Word Access120TABLE 11-2: User ID, Device ID and Configuration Word Access (CFGS = 1)12011.6 Write Verify121EXAMPLE 11-6: EEPROM Write Verify12111.7 Register Definitions: Data EEPROM Control122Register 11-1: EEDATL: EEPROM Data Low Byte Register122Register 11-2: EEDATH: EEPROM Data High Byte Register122Register 11-3: EEADRL: EEPROM Address Low Byte Register123Register 11-4: EEADRH: EEPROM Address High Byte Register123Register 11-5: EECON1: EEPROM Control 1 Register124Register 11-6: EECON2: EEPROM Control 2 Register125TABLE 11-3: Summary of Registers Associated with Data EEPROM12512.0 I/O Ports127TABLE 12-1: Port Availability Per Device127FIGURE 12-1: Generic I/O Port Operation127EXAMPLE 12-1: Initializing PORTA12712.1 Alternate Pin Function12812.2 Register Definitions: Alternate Pin Function Control129Register 12-1: APFCON: Alternate Pin Function Control Register12912.3 PORTA Registers13012.3.1 ANSELA Register13012.3.2 PORTA Functions and Output Priorities130TABLE 12-2: PORTA Output Priority13012.4 Register Definitions: PORTA131Register 12-2: PORTA: PORTA Register131Register 12-3: TRISA: PORTA Tri-State Register131Register 12-4: LATA: PORTA Data Latch Register131Register 12-5: ANSELA: PORTA Analog Select Register132TABLE 12-3: Summary of Registers Associated with PORTA132TABLE 12-4: Summary of Configuration Word with PORTA13212.5 PORTB Registers13312.5.1 Weak Pull-Ups13312.5.2 Interrupt-on-Change13312.5.3 PORTB Functions and Output Priorities133TABLE 12-5: PORTB Output Priority13312.6 Register Definitions: PORTB134Register 12-6: PORTB: PORTB Register134Register 12-7: TRISB: PORTB Tri-State Register134Register 12-8: LATB: PORTB Data Latch Register134Register 12-9: WPUB: Weak Pull-up PORTB Register135TABLE 12-6: Summary of Registers Associated with PORTB13512.7 PORTC Registers13612.7.1 PORTC Functions and Output Priorities136TABLE 12-7: PORTC Output Priority13612.8 Register Definitions: PORTC137Register 12-10: PORTC: PORTC Register137Register 12-11: TRISC: PORTC Tri-State Register137Register 12-12: LATC: PORTC Data Latch Register137TABLE 12-8: Summary of Registers Associated with PORTC13812.9 PORTD Registers13912.9.1 PORTD Functions and Output Priorities139TABLE 12-9: PORTD Output Priority13912.10 Register Definitions: PORTD140Register 12-13: PORTD: PORTD Register140Register 12-14: TRISD: PORTD Tri-State Register140Register 12-15: LATD: PORTD Data Latch Register140TABLE 12-10: Summary of Registers Associated with PORTD14112.11 PORTE Registers14212.11.1 ANSELE Register14212.11.2 PORTE Functions and Output Priorities142TABLE 12-11: PORTE Output Priority14212.12 Register Definitions: PORTE143Register 12-16: PORTE: PORTE Register143Register 12-17: TRISE: PORTE Tri-State Register143Register 12-18: LATE: PORTE Data Latch Register144Register 12-19: ANSELE: PORTE Analog Select Register144TABLE 12-12: Summary of Registers Associated with PORTE14412.13 PORTF Registers14512.13.1 ANSELF Register14512.13.2 PORTF Functions and Output Priorities145TABLE 12-13: PORTF Output Priority14512.14 Register Definitions: PORTF146Register 12-20: PORTF: PORTF Register146Register 12-21: TRISF: PORTF Tri-State Register146Register 12-22: LATF: PORTF Data Latch Register146Register 12-23: ANSELF: PORTF Analog Select Register147TABLE 12-14: Summary of Registers Associated with PORTF147TABLE 12-15: Summary of Configuration Word Associated with PORTF14712.15 PORTG Registers14812.15.1 ANSELG Register14812.15.2 PORTG Functions and Output Priorities148TABLE 12-16: PORTG Output Priority14812.16 Register Definitions: PORTG149Register 12-24: PORTG: PORTG Register149Register 12-25: TRISG: PORTG Tri-State Register149Register 12-26: LATG: PORTG Data Latch Register149Register 12-27: ANSELG: PORTG Analog Select Register150Register 12-28: WPUG: Weak Pull-up PORTG Register150TABLE 12-17: Summary of Registers Associated with PORTG15113.0 Interrupt-On-Change15313.1 Enabling the Module15313.2 Individual Pin Configuration15313.3 Interrupt Flags15313.4 Clearing Interrupt Flags153EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)15313.5 Operation in Sleep153FIGURE 13-1: Interrupt-On-Change Block Diagram15413.6 Register Definitions: Interrupt-on-Change Control155Register 13-1: IOCBP: Interrupt-on-Change PORTB Positive Edge Register155Register 13-2: IOCBN: Interrupt-on-Change PORTB Negative Edge Register155Register 13-3: IOCBF: Interrupt-on-Change PORTB Flag Register155TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change15614.0 Fixed Voltage Reference (FVR)15714.1 Independent Gain Amplifiers15714.2 FVR Stabilization Period157FIGURE 14-1: Voltage Reference Block Diagram15714.3 Register Definitions: FVR Control158Register 14-1: FVRCON: Fixed Voltage Reference Control Register158TABLE 14-1: Summary of Registers Associated with the Fixed Voltage Reference15815.0 Temperature Indicator Module15915.1 Circuit Operation159EQUATION 15-1: Vout Ranges159FIGURE 15-1: Temperature Circuit Diagram15915.2 Minimum Operating Vdd159TABLE 15-1: Recommended Vdd vs. Range15915.3 Temperature Output15915.4 ADC Acquisition Time160TABLE 15-2: Summary of Registers Associated with the Temperature Indicator16016.0 Analog-to-Digital Converter (ADC) Module161FIGURE 16-1: ADC Block Diagram16216.1 ADC Configuration16316.1.1 Port Configuration16316.1.2 Channel Selection16316.1.3 ADC Voltage Reference16316.1.4 Conversion Clock163TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies164FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles16416.1.5 Interrupts16516.1.6 Result Formatting165FIGURE 16-3: 10-Bit A/D Conversion Result Format16516.2 ADC Operation16616.2.1 Starting a Conversion16616.2.2 Completion of a Conversion16616.2.3 Terminating a conversion16616.3 ADC Operation During Sleep16616.3.1 Special Event Trigger166TABLE 16-2: Special Event Trigger16616.3.2 A/D Conversion Procedure167EXAMPLE 16-1: A/D Conversion16716.4 Register Definitions: ADC Control168Register 16-1: ADCON0: A/D Control Register 0168Register 16-2: ADCON1: A/D Control Register 1169Register 16-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0170Register 16-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0170Register 16-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1171Register 16-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 117116.5 A/D Acquisition Requirements172EQUATION 16-1: Acquisition Time Example172FIGURE 16-4: Analog Input Model173FIGURE 16-5: ADC Transfer Function173TABLE 16-3: Summary of Registers Associated with ADC17417.0 Digital-to-Analog Converter (DAC) Module17517.1 Output Voltage Selection175EQUATION 17-1: DAC Output Voltage17517.2 Ratiometric Output Level17517.3 DAC Voltage Reference Output175FIGURE 17-1: Digital-to-Analog Converter Block Diagram176FIGURE 17-2: Voltage Reference Output Buffer Example17617.4 Low-Power Voltage State17717.4.1 Output Clamped to Positive Voltage Source17717.4.2 Output Clamped to Negative Voltage Source177FIGURE 17-3: Output Voltage Clamping Examples17717.5 Operation During Sleep17717.6 Effects of a Reset17717.7 Register Definitions: DAC Control178Register 17-1: DACCON0: Voltage Reference Control Register 0178Register 17-2: DACCON1: Voltage Reference Control Register 1178TABLE 17-1: Summary of Registers Associated with the DAC Module17818.0 Comparator Module17918.1 Comparator Overview179TABLE 18-1: Comparator Availability Per Device179FIGURE 18-1: Single Comparator179FIGURE 18-2: Comparator Module Simplified Block Diagram18018.2 Comparator Control18118.2.1 Comparator Enable18118.2.2 Comparator Output Selection18118.2.3 Comparator Output Polarity181TABLE 18-2: Comparator Output State vs. Input Conditions18118.2.4 Comparator Speed/Power Selection18118.3 Comparator Hysteresis18218.4 Timer1 Gate Operation18218.4.1 Comparator Output Synchronization18218.5 Comparator Interrupt18218.6 Comparator Positive Input Selection18218.7 Comparator Negative Input Selection18318.8 Comparator Response Time18318.9 Interaction with ECCP Logic18318.10 Analog Input Connection Considerations183FIGURE 18-3: Analog Input Model18418.11 Register Definitions: Comparator Control185Register 18-1: CMxCON0: Comparator Cx Control Register 0185Register 18-2: CMxCON1: Comparator Cx Control Register 1186Register 18-3: CMOUT: Comparator Output Register186TABLE 18-3: Summary of Registers Associated with Comparator Module18719.0 SR Latch18919.1 Latch Operation18919.2 Latch Output18919.3 Effects of a Reset189FIGURE 19-1: SR Latch Simplified Block Diagram190TABLE 19-1: SRCLK Frequency table19119.4 Register Definitions: SR Latch Control192Register 19-1: SRCON0: SR Latch Control 0 Register192Register 19-2: SRCON1: SR Latch Control 1 Register193TABLE 19-2: Summary of Registers Associated with SR Latch Module19320.0 Timer0 Module19520.1 Timer0 Operation19520.1.1 8-bit Timer mode19520.1.2 8-Bit Counter Mode195FIGURE 20-1: Block Diagram of the Timer019520.1.3 Software Programmable Prescaler19620.1.4 Timer0 Interrupt19620.1.5 8-Bit Counter Mode Synchronization19620.1.6 Operation During Sleep19620.2 Register Definitions: Option Register197Register 20-1: OPTION_REG: OPTION Register197TABLE 20-1: Summary of Registers Associated with Timer019721.0 Timer1 Module with Gate Control199FIGURE 21-1: Timer1 Block Diagram19921.1 Timer1 Operation200TABLE 21-1: Timer1 Enable Selections20021.2 Clock Source Selection20021.2.1 Internal Clock Source20021.2.2 External Clock Source200TABLE 21-2: Clock Source Selections20021.3 Timer1 Prescaler20121.4 Timer1 Oscillator20121.5 Timer1 Operation in Asynchronous Counter Mode20121.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode20121.6 Timer1 Gate20121.6.1 Timer1 Gate Enable201TABLE 21-3: Timer1 Gate Enable Selections20121.6.2 Timer1 Gate Source Selection202TABLE 21-4: Timer1 Gate Sources20221.6.3 Timer1 Gate Toggle Mode20221.6.4 Timer1 Gate Single-Pulse Mode20221.6.5 Timer1 Gate Value Status20221.6.6 Timer1 Gate Event Interrupt20221.7 Timer1 Interrupt20321.8 Timer1 Operation During Sleep20321.9 ECCP/CCP Capture/Compare Time Base20321.10 ECCP/CCP Special Event Trigger203FIGURE 21-2: Timer1 Incrementing Edge203FIGURE 21-3: Timer1 Gate Enable Mode204FIGURE 21-4: Timer1 Gate Toggle Mode204FIGURE 21-5: Timer1 Gate Single-Pulse Mode205FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode20621.11 Register Definitions: Timer1 Control207Register 21-1: T1CON: Timer1 Control Register207Register 21-2: T1GCON: Timer1 Gate Control Register208TABLE 21-5: Summary of Registers Associated with Timer120922.0 Timer2/4/6 Modules211FIGURE 22-1: Timer2/4/6 Block Diagram21122.1 Timer2/4/6 Operation21222.2 Timer2/4/6 Interrupt21222.3 Timer2/4/6 Output21222.4 Timer2/4/6 Operation During Sleep21222.5 Register Definitions: Timer2 Control213Register 22-1: TxCON: Timer2/Timer4/Timer6 Control Register213TABLE 22-1: Summary of Registers Associated With Timer2/4/621423.0 Capture/Compare/PWM Modules215TABLE 23-1: PWM Resources21523.1 Capture Mode21623.1.1 CCP pin Configuration216FIGURE 23-1: Capture Mode Operation Block Diagram21623.1.2 Timer1 Mode Resource21623.1.3 Software Interrupt Mode21623.1.4 CCP Prescaler216EXAMPLE 23-1: Changing Between Capture Prescalers21623.1.5 Capture During Sleep21723.1.6 Alternate Pin Locations217TABLE 23-2: Summary of Registers Associated with Capture21723.2 Compare Mode218FIGURE 23-2: Compare Mode Operation Block Diagram21823.2.1 CCP Pin Configuration21823.2.2 Timer1 Mode Resource21823.2.3 Software Interrupt Mode21823.2.4 Special Event Trigger218TABLE 23-3: Special Event Trigger21823.2.5 Compare During Sleep21923.2.6 Alternate Pin Locations219TABLE 23-4: Summary of Registers Associated with Compare21923.3 PWM Overview22023.3.1 Standard PWM Operation220FIGURE 23-3: CCP PWM Output Signal220FIGURE 23-4: Simplified PWM Block Diagram22023.3.2 Setup for PWM Operation22123.3.3 Timer2/4/6 Timer Resource22123.3.4 PWM Period221EQUATION 23-1: PWM Period22123.3.5 PWM Duty Cycle221EQUATION 23-2: Pulse Width221EQUATION 23-3: Duty Cycle Ratio22123.3.6 PWM Resolution222EQUATION 23-4: PWM Resolution222TABLE 23-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)222TABLE 23-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)222TABLE 23-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)22223.3.7 Operation in Sleep Mode22323.3.8 Changes in System Clock Frequency22323.3.9 Effects of Reset22323.3.10 Alternate Pin Locations223TABLE 23-8: Summary of Registers Associated with Standard PWM22323.4 PWM (Enhanced Mode)224FIGURE 23-5: Example Simplified Block Diagram of the Enhanced PWM Mode224TABLE 23-9: Example Pin Assignments for Various PWM Enhanced Modes225FIGURE 23-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)225FIGURE 23-7: Example Enhanced PWM Output Relationships (Active-Low State)22623.4.1 Half-Bridge Mode227FIGURE 23-8: Example of Half-Bridge PWM Output227FIGURE 23-9: Example of Half-Bridge Applications22723.4.2 Full-Bridge Mode228FIGURE 23-10: Example of Full-Bridge Application228FIGURE 23-11: Example of Full-Bridge PWM Output229FIGURE 23-12: Example of PWM Direction Change230FIGURE 23-13: Example of PWM Direction Change at Near 100% Duty Cycle23123.4.3 Enhanced PWM Auto-shutdown mode232FIGURE 23-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)23323.4.4 Auto-Restart Mode233FIGURE 23-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)23323.4.5 Programmable Dead-Band Delay Mode234FIGURE 23-16: Example of Half-Bridge PWM Output234FIGURE 23-17: Example of Half-Bridge Applications23423.4.6 PWM Steering Mode235FIGURE 23-18: Simplified Steering Block Diagram23523.4.7 Start-up Considerations236FIGURE 23-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)236FIGURE 23-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)23623.4.8 Alternate Pin Locations237TABLE 23-10: Summary of Registers Associated with Enhanced PWM23723.5 Register Definitions: ECCP Control238Register 23-1: CCPXCON: CCPx Control Register238Register 23-2: CCPTMRS0: PWM Timer Selection Control Register 0239Register 23-3: CCPTMRS1: PWM Timer Selection Control Register 1239Register 23-4: CCPxAS: CCPx Auto-Shutdown Control Register240Register 23-5: PWMxCON: Enhanced PWM Control Register241Register 23-6: PSTRxCON: PWM Steering Control Register(1)24224.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module24324.1 Master SSPx (MSSPx) Module Overview243FIGURE 24-1: MSSPx Block Diagram (SPI mode)243FIGURE 24-2: MSSPx Block Diagram (I2C™ Master mode)244FIGURE 24-3: MSSPx Block Diagram (I2C™ Slave mode)24524.2 SPI Mode Overview246FIGURE 24-4: SPI Master and Multiple Slave Connection24724.2.1 SPI Mode Registers24724.2.2 SPI Mode Operation248FIGURE 24-5: SPI Master/Slave Connection24824.2.3 SPI Master Mode249FIGURE 24-6: SPI Mode Waveform (Master Mode)24924.2.4 SPI Slave Mode25024.2.5 Slave Select Synchronization250FIGURE 24-7: SPI Daisy-Chain Connection251FIGURE 24-8: slave Select Synchronous Waveform251FIGURE 24-9: SPI Mode Waveform (Slave Mode With CKE = 0)252FIGURE 24-10: SPI Mode Waveform (SLAve Mode With CKE = 1)25224.2.6 SPI Operation In Sleep Mode253TABLE 24-1: Summary of Registers Associated with SPI Operation25324.3 I2C Mode Overview254FIGURE 24-11: I2C Master/ Slave Connection25424.3.1 Clock Stretching25524.3.2 Arbitration25524.4 I2C Mode Operation25524.4.1 Byte Format25524.4.2 Definition of I2C Terminology25524.4.3 SDAx and SCLx PINS25524.4.4 SDAx Hold Time256TABLE 24-2: I2C Bus terms25624.4.5 Start Condition25724.4.6 STOP Condition25724.4.7 Restart Condition25724.4.8 START/STOP Condition Interrupt masking257FIGURE 24-12: I2C START and STOP Conditions257FIGURE 24-13: I2C Restart Condition25724.4.9 Acknowledge Sequence25824.5 I2C Slave Mode Operation25824.5.1 Slave Mode Addresses25824.5.2 Slave Reception259FIGURE 24-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)260FIGURE 24-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)261FIGURE 24-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)262FIGURE 24-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)26324.5.3 SLAVE Transmission264FIGURE 24-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)265FIGURE 24-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)26724.5.4 Slave mode 10-bit Address Reception26824.5.5 10-bit Addressing With Address Or Data Hold268FIGURE 24-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)269FIGURE 24-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)270FIGURE 24-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)27124.5.6 Clock Stretching27224.5.7 Clock Synchronization and the CKP Bit272FIGURE 24-23: Clock Synchronization Timing27224.5.8 General Call Address Support273FIGURE 24-24: Slave Mode General call address sequence27324.5.9 SSPx Mask Register27324.6 I2C Master Mode27424.6.1 I2C Master Mode Operation27424.6.2 Clock Arbitration275FIGURE 24-25: Baud Rate Generator Timing with Clock Arbitration27524.6.3 WCOL Status Flag27524.6.4 I2C Master Mode Start Condition Timing276FIGURE 24-26: First Start Bit Timing27624.6.5 I2C Master Mode Repeated Start Condition Timing277FIGURE 24-27: Repeat Start Condition Waveform27724.6.6 I2C Master Mode Transmission278FIGURE 24-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)27924.6.7 I2C Master Mode Reception280FIGURE 24-29: I2C Master Mode Waveform (Reception, 7-Bit Address)28124.6.8 Acknowledge Sequence Timing28224.6.9 Stop Condition Timing282FIGURE 24-30: Acknowledge Sequence Waveform282FIGURE 24-31: Stop Condition Receive or Transmit Mode28324.6.10 Sleep Operation28324.6.11 Effects of a Reset28324.6.12 Multi-Master Mode28324.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration283FIGURE 24-32: Bus Collision Timing for Transmit and Acknowledge284FIGURE 24-33: Bus Collision During Start Condition (SDAx Only)285FIGURE 24-34: Bus Collision During Start Condition (SCLx = 0)286FIGURE 24-35: BRG Reset Due to Sda Arbitration During Start Condition286FIGURE 24-36: Bus Collision During a Repeated Start Condition (Case 1)287FIGURE 24-37: Bus Collision During Repeated Start Condition (Case 2)287FIGURE 24-38: Bus Collision During a Stop Condition (Case 1)288FIGURE 24-39: Bus Collision During a Stop Condition (Case 2)288TABLE 24-3: Summary of Registers Associated with I2C™ Operation28924.7 Baud Rate Generator290FIGURE 24-40: Baud Rate Generator Block Diagram290TABLE 24-4: MSSPx Clock Rate w/BRG29024.8 Register Definitions: MSSP Control291Register 24-1: SSPxSTAT: SSPx STATUS Register291Register 24-2: SSPxCON1: SSPx Control Register 1292Register 24-3: SSPxCON2: SSPx Control Register 2294Register 24-4: SSPxCON3: SSPx Control Register 3295Register 24-5: SSPxMSK: SSPx Mask Register296Register 24-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode)29625.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)297FIGURE 25-1: EUSART Transmit Block Diagram297FIGURE 25-2: EUSART Receive Block Diagram29825.1 EUSART Asynchronous Mode29925.1.1 EUSART Asynchronous Transmitter299FIGURE 25-3: Asynchronous Transmission300FIGURE 25-4: Asynchronous Transmission (Back-to-Back)301TABLE 25-1: Registers Associated with Asynchronous Transmission30125.1.2 EUSART Asynchronous Receiver302FIGURE 25-5: Asynchronous Reception305TABLE 25-2: Registers Associated with Asynchronous Reception30525.2 Clock Accuracy with Asynchronous Operation30625.3 Register Definitions: EUSART Control307Register 25-1: TXxSTA: Transmit Status And Control Register307Register 25-2: RCxSTA: Receive Status and Control Register308Register 25-3: BAUDxCON: Baud Rate Control Register30925.4 EUSART Baud Rate Generator (BRG)310EXAMPLE 25-1: Calculating Baud Rate Error310TABLE 25-3: Baud Rate Formulas310TABLE 25-4: Registers Associated with Baud Rate Generator311TABLE 25-5: Baud Rates for Asynchronous Modes31125.4.1 Auto-Baud Detect314TABLE 25-6: BRG Counter Clock Rates314FIGURE 25-6: Automatic Baud Rate Calibration31425.4.2 Auto-baud Overflow31525.4.3 Auto-Wake-up on Break315FIGURE 25-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation316FIGURE 25-8: Auto-Wake-up Bit (WUE) Timings During Sleep31625.4.4 Break Character Sequence31725.4.5 Receiving a Break Character317FIGURE 25-9: Send Break Character Sequence31725.5 EUSART Synchronous Mode31825.5.1 Synchronous Master Mode318FIGURE 25-10: Synchronous Transmission319FIGURE 25-11: Synchronous Transmission (Through TXEN)319TABLE 25-7: Registers Associated with Synchronous Master Transmission320FIGURE 25-12: Synchronous Reception (Master Mode, SREN)322TABLE 25-8: Registers Associated with Synchronous Master Reception32225.5.2 Synchronous Slave Mode323TABLE 25-9: Registers Associated with Synchronous Slave Transmission324TABLE 25-10: Registers Associated with Synchronous Slave Reception32526.0 Capacitive Sensing (CPS) Module327FIGURE 26-1: Capacitive Sensing Block Diagram327FIGURE 26-2: Capacitive Sensing Oscillator Block Diagram32826.1 Analog MUX32926.2 Capacitive Sensing Oscillator32926.2.1 Voltage Reference Modes32926.2.2 Current Ranges330TABLE 26-1: Power Mode Selection33026.2.3 Timer Resources33026.2.4 Fixed Time Base330TABLE 26-2: Timer1 Enable Function33126.2.5 Software Control33126.3 Operation during Sleep33226.4 Register Definitions: Capacitive Sensing Control333Register 26-1: CPSCON0: Capacitive Sensing Control Register 0333Register 26-2: CPSCON1: Capacitive Sensing Control Register 1334TABLE 26-3: Summary of Registers Associated with Capacitive Sensing33427.0 Liquid Crystal Display (LCD) Driver Module33527.1 LCD Registers335FIGURE 27-1: LCD Driver Module Block Diagram335TABLE 27-1: LCD Segment and Data Registers33627.2 Register Definitions: Liquid Crystal Display (LCD) Control337Register 27-1: LCDCON: Liquid Crystal Display (LCD) Control Register337Register 27-2: LCDPS: LCD Phase Register338Register 27-3: LCDREF: LCD Reference Voltage Control Register339Register 27-4: LCDCST: LCD Contrast Control Register340Register 27-5: LCDSEn: LCD Segment Enable Registers341Register 27-6: LCDDATAn: LCD Data Registers34127.3 LCD Clock Source Selection34227.3.1 LCD Prescaler342FIGURE 27-2: LCD Clock Generation34227.4 LCD Bias Voltage Generation343TABLE 27-2: LCD Bias Voltages343FIGURE 27-3: LCD Bias VOltage Generation Block DIagram34327.5 LCD Bias Internal Reference Ladder34427.5.1 Bias Mode Interaction344TABLE 27-3: LCD Internal Ladder Power Modes (1/3 Bias)34427.5.2 Power Modes34427.5.3 Automatic power mode switching345FIGURE 27-4: LCD Internal Reference Ladder Power Mode Switching Diagram – Type A345FIGURE 27-5: LCD Internal Reference Ladder Power Mode Switching Diagram – Type A Waveform (1/2 Mux, 1/2 Bias Drive)346FIGURE 27-6: LCD Internal Reference Ladder Power Mode Switching Diagram – Type B Waveform (1/2 Mux, 1/2 Bias Drive)34727.6 Register Definitions: LCD Ladder Control348Register 27-7: LCDRL: LCD Reference Ladder Control Registers34827.6.1 Contrast Control349FIGURE 27-7: Internal Reference and Contrast Control Block Diagram34927.6.2 Internal Reference34927.6.3 VLCD<3:1> pins34927.7 LCD Multiplex Types350TABLE 27-4: Common Pin Usage35027.8 Segment Enables35027.9 Pixel Control35027.10 LCD Frame Frequency350TABLE 27-5: Frame Frequency Formulas350TABLE 27-6: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or LFINTOSC350TABLE 27-7: LCD Segment Mapping Worksheet35127.11 LCD Waveform Generation352FIGURE 27-8: Type-A/Type-B Waveforms in Static Drive352FIGURE 27-9: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive353FIGURE 27-10: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive354FIGURE 27-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive355FIGURE 27-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive356FIGURE 27-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive357FIGURE 27-14: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive358FIGURE 27-15: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive359FIGURE 27-16: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive360FIGURE 27-17: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive361FIGURE 27-18: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive36227.12 LCD Interrupts36327.12.1 LCD Interrupt on Module Shutdown36327.12.2 LCD Frame Interrupts363FIGURE 27-19: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example – Type-B, Non-Static)36427.13 Operation During Sleep365TABLE 27-8: LCD Module Status During Sleep365FIGURE 27-20: Sleep Entry/Exit when SLPEN = 136627.14 Configuring the LCD Module36727.15 Disabling the LCD Module36727.16 LCD Current Consumption36727.16.1 Oscillator Selection36727.16.2 LCD Bias Source36727.16.3 Capacitance of the LCD segments367TABLE 27-9: Summary of Registers Associated with LCD Operation36828.0 In-Circuit Serial Programming™ (ICSP™)37128.1 High-Voltage Programming Entry Mode371FIGURE 28-1: Vpp Limiter Example Circuit37128.2 Low-Voltage Programming Entry Mode37228.3 Common Programming Interfaces372FIGURE 28-2: ICD RJ-11 Style Connector Interface372FIGURE 28-3: PICkit™ Programmer Style Connector Interface372FIGURE 28-4: Typical connection for ICSP™ programming37329.0 Instruction Set Summary37529.1 Read-Modify-Write Operations375TABLE 29-1: Opcode Field Descriptions375TABLE 29-2: Abbreviation Descriptions375FIGURE 29-1: General Format for Instructions376TABLE 29-3: PIC16(L)F1946/47 Instruction Set377TABLE 29-3: PIC16(L)F1946/47 Enhanced Instruction Set (Continued)37829.2 Instruction Descriptions37930.0 Electrical Specifications389Absolute Maximum Ratings(†)389FIGURE 30-1: PIC16F1946/47 Voltage Frequency Graph, -40°C £ Ta £ +125°C390FIGURE 30-2: PIC16LF1946/47 Voltage Frequency Graph, -40°C £ Ta £ +125°C390FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature39130.1 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended)392FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd39330.2 DC Characteristics: PIC16(L)F1946/47-I/E (Industrial, Extended)39430.3 DC Characteristics: PIC16(L)F1946/47-I/E (Power-Down)39730.4 DC Characteristics: PIC16(L)F1946/47-I/E40030.5 Memory Programming Requirements40130.6 Thermal Considerations40230.7 Timing Parameter Symbology403FIGURE 30-5: Load Conditions40330.8 AC Characteristics: PIC16(L)F1946/47-I/E404FIGURE 30-6: Clock Timing404TABLE 30-1: Clock Oscillator Timing Requirements404TABLE 30-2: Oscillator Parameters405TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)405FIGURE 30-7: CLKOUT and I/O Timing405TABLE 30-4: CLKOUT and I/O Timing Parameters406FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing406FIGURE 30-9: Brown-Out Reset Timing and Characteristics407TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters408FIGURE 30-10: Timer0 and Timer1 External Clock Timings408TABLE 30-6: Timer0 and Timer1 External Clock Requirements409FIGURE 30-11: Capture/Compare/PWM Timings (CCP)409TABLE 30-7: Capture/Compare/PWM Requirements (CCP)409TABLE 30-8: PIC16(L)F1946/47 A/D Converter (ADC) Characteristics(1,2,3):410TABLE 30-9: PIC16(L)F1946/47 A/D Conversion Requirements410FIGURE 30-12: PIC16(L)F1946/47 A/D Conversion Timing (Normal Mode)411FIGURE 30-13: PIC16(L)F1946/47 A/D Conversion Timing (Sleep Mode)411TABLE 30-10: Comparator Specifications412TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications412FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing412TABLE 30-12: USART Synchronous Transmission Requirements413FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing413TABLE 30-13: USART Synchronous Receive Requirements413FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)414FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)414FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)415FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)415TABLE 30-14: SPI Mode requirements416FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing416TABLE 30-15: I2C™ Bus Start/Stop Bits Requirements417FIGURE 30-21: I2C™ Bus Data Timing417TABLE 30-16: I2C™ Bus Data Requirements418TABLE 30-17: Cap Sense Oscillator Specifications419FIGURE 30-22: Cap Sense Oscillator41931.0 DC and AC Characteristics Graphs and Charts421FIGURE 31-1: Idd, LP Oscillator Mode, Fosc = 32 kHz, PIC16LF1946/47 Only422FIGURE 31-2: Idd, LP Oscillator Mode, Fosc = 32 kHz, PIC16F1946/47 only422FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1946/47 only423FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1946/47 only423FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1946/47 only424FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1946/47 only424FIGURE 31-7: Idd, EC Oscillator, Low-Power Mode, Fosc = 32 kHz, PIC16LF1946/47 only425FIGURE 31-8: Idd, EC Oscillator, Low-Power Mode, Fosc = 32 kHz, PIC16F1946/47 only425FIGURE 31-9: Idd, EC Oscillator, Low-Power Mode, Fosc = 500 kHz, PIC16LF1946/47 only426FIGURE 31-10: Idd, EC Oscillator, Low-Power Mode, Fosc = 500 kHz, PIC16F1946/47 only426FIGURE 31-11: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16LF1946/47 only427FIGURE 31-12: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16LF1946/47 only427FIGURE 31-13: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16F1946/47 only428FIGURE 31-14: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16F1946/47 only428FIGURE 31-15: Idd Typical, EC Oscillator, High-Power Mode, PIC16LF1946/47 only429FIGURE 31-16: Idd Maximum, EC Oscillator, High-Power Mode, PIC16LF1946/47 only429FIGURE 31-17: Idd Typical, EC Oscillator, High-Power Mode, PIC16F1946/47 only430FIGURE 31-18: Idd Maximum, EC Oscillator, High-Power Mode, PIC16F1946/47 only430FIGURE 31-19: Idd, LFINTOSC Mode, Fosc = 32 kHz, PIC16LF1946/47 only431FIGURE 31-20: Idd, LFINTOSC Mode, Fosc = 32 kHz, PIC16F1946/47 only431FIGURE 31-21: Idd, MFINTOSC Mode, Fosc = 500 kHz, PIC16LF1946/47 only432FIGURE 31-22: Idd, MFINTOSC Mode, Fosc = 500 kHz, PIC16F1946/47 only432FIGURE 31-23: Idd Typical, HFINTOSC Mode, PIC16LF1946/47 only433FIGURE 31-24: Idd Maximum, HFINTOSC Mode, PIC16LF1946/47 only433FIGURE 31-25: Idd Typical, HFINTOSC Mode, PIC16F1946/47 only434FIGURE 31-26: Idd Maximum, HFINTOSC Mode, PIC16F1946/47 only434FIGURE 31-27: Idd Typical, HS Oscillator, PIC16LF1946/47 only435FIGURE 31-28: Idd Maximum, HS Oscillator, PIC16LF1946/47 only435FIGURE 31-29: Idd Typical, HS Oscillator, PIC16F1946/47 only436FIGURE 31-30: Idd Maximum, HS Oscillator, PIC16F1946/47 only436FIGURE 31-31: Ipd Base, PIC16LF1946/47 only437FIGURE 31-32: Ipd Base, PIC16F1946/47 only437FIGURE 31-33: Ipd, Watchdog Timer (WDT), PIC16LF1946/47 only438FIGURE 31-34: Ipd, Watchdog Timer (WDT), PIC16F1946/47 only438FIGURE 31-35: Ipd, Fixed Voltage Reference (FVR), PIC16LF1946/47 only439FIGURE 31-36: Ipd, Fixed Voltage Reference (FVR), PIC16F1946/47 only439FIGURE 31-37: Ipd, Brown-Out Reset (BOR), PIC16LF1946/47 only440FIGURE 31-38: Ipd, Brown-Out Reset (BOR), PIC16F1946/47 only440FIGURE 31-39: Ipd, Timer1 Oscillator, Fosc = 32 kHz, PIC16LF1946/47 only441FIGURE 31-40: Ipd, Timer1 Oscillator, Fosc = 32 kHz, PIC16F1946/47 only441FIGURE 31-41: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16LF1946/47 only442FIGURE 31-42: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16F1946/47 only442FIGURE 31-43: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16LF1946/47 only443FIGURE 31-44: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16F1946/47 only443FIGURE 31-45: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16LF1946/47 only444FIGURE 31-46: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16F1946/47 only444FIGURE 31-47: Ipd, Comparator, Low-Power Mode, PIC16LF1946/47 only445FIGURE 31-48: Ipd, Comparator, Low-Power Mode, PIC16F1946/47 only445FIGURE 31-49: Ipd, Comparator, High-Power Mode, PIC16LF1946/47 only446FIGURE 31-50: Ipd, Comparator, High-Power Mode, PIC16F1946/47 only446FIGURE 31-51: Voh vs. Ioh Over Temperature, Vdd = 5.0V, PIC16F1946/47 only447FIGURE 31-52: Vol vs. Iol Over Temperature, Vdd = 5.0V, PIC16F1946/47 only447FIGURE 31-53: Voh vs. Ioh Over Temperature, Vdd = 3.0V448FIGURE 31-54: Vol vs. Iol Over Temperature, Vdd = 3.0V448FIGURE 31-55: Voh vs. Ioh Over Temperature, Vdd = 1.8V449FIGURE 31-56: Vol vs. Iol Over Temperature, Vdd = 1.8V449FIGURE 31-57: Brown-out Reset Voltage, BORV = 1450FIGURE 31-58: Brown-out Reset Hysteresis, BORV = 1450FIGURE 31-59: Brown-out Reset Voltage, BORV = 0451FIGURE 31-60: Brown-out Reset Hysteresis, BORV = 0451FIGURE 31-61: Comparator Hysteresis, High-Power Mode452FIGURE 31-62: Comparator Hysteresis, Low-Power Mode452FIGURE 31-63: Comparator Response Time, High-Power Mode453FIGURE 31-64: Comparator Response Time Over Temperature, High-Power Mode453FIGURE 31-65: Comparator Input Offset at 25°C, High-Power Mode, PIC16F1946/47 only45432.0 Development Support45533.0 Packaging Information45933.1 Package Marking Information45933.2 Package Details460Appendix A: Data Sheet Revision History465Revision A (3/2010)465Revision B (9/2010)465Revision C (5/2011)465Revision D (02/2012)465Appendix B: Migrating From Other PIC® Devices465TABLE B-1: Feature Comparison465INDEX467The Microchip Web Site475Customer Change Notification Service475Customer Support475Reader Response476Product Identification System477Worldwide Sales478サイズ： 4.73MBページ数： 478Language: Englishマニュアルを開く
ユーザーズマニュアル目次Chapter 1. F1 LV Evaluation Platform Overview111.1 Introduction111.2 Platform Contents111.3 Hardware Features111.3.1 PIC16LF1947111.3.2 MCP9800 I2C™ Temperature Sensor111.3.3 PICkit™ 3 Programming/Debug Header121.3.4 MCP2200 USB to Serial Converter121.3.5 Two Push Buttons, One Potentiometer, 7 LEDs121.3.6 One Custom LCD121.3.7 20-pin Add-on Connector121.3.8 Current Monitoring Connector121.3.9 Generous Prototyping Area121.3.10 MCP1640 Synchronous Boost Regulator121.3.11 MCP1703 LDO Regulator121.3.12 User Selectable Power Sources13Chapter 2. Getting Started152.1 Introduction15Figure 2-1: F1 LV Evaluation Platform152.2 Powering the F1 LV Evaluation Platform162.3 Powering with PICkit™ 316Figure 2-2: Powering from PICkit™ 3162.4 Powering from External Power Supply17Figure 2-3: Powering with External Power Supply172.5 Powering with the ADD-on Expansion Header J318Figure 2-4: Expansion Slot Power182.6 Powering with a AAA Battery18Figure 2-5: Powering from Battery182.7 Powering with a USB Cable19Figure 2-6: USB POWER192.8 Default Firmware192.8.1 Blinking LEDs192.8.2 Measuring the Ambient Temperature192.8.3 Add-on Motor Expansion202.8.4 LCD Display202.8.5 User Interface20Chapter 3. Programming the F1 LV Evaluation Platform213.1 Introduction213.2 Programming/Development Tool Support213.3 Hardware Resources22Table 3-1: hARDWARE rESOURCES22Chapter 4. Demo Code254.1 Introduction254.2 Service Drivers254.3 Combined Demo254.4 Motor Control GUI Application254.5 BLDC Demo254.6 BDC Demo264.7 Unipolar Stepper Demo264.8 Bipolar Stepper Demo26Chapter 5. Hardware Libraries and Drivers275.1 Introduction275.2 I2C™ Driver275.3 MCP9800 Driver275.4 RTCC Driver275.5 LCD Driver275.6 Using the I2C™ Driver285.6.1 I2C Data Structures285.6.1.1 I2C_RESULTS28Table 5-1: I2C_RESULTS_T285.6.1.2 I2C_TRANSACTION_REQUEST_BLOCK285.6.2 I2C Function Interface295.6.2.1 i2c_init29Figure 5-1:295.6.2.2 i2c_insert29Figure 5-2:295.6.2.3 i2c_build_write_trb / i2c_build_read_trb29Figure 5-3:295.6.2.4 i2c_write_block / i2c_read_block29Figure 5-4:305.6.2.5 i2c_handler30Figure 5-5:305.7 Using the LCD driver305.7.1 LCD Data Structures305.7.1.1 BCD_TYPE30Figure 5-6:305.7.2 LCD Function Interface315.7.2.1 lcd_init31Figure 5-7:315.7.2.2 lcd_display_digits31Figure 5-8:315.7.2.3 lcd_display_on/lcd_display_off31Figure 5-9:315.7.3 LCD Segment Definitions32Figure 5-10: LCD Display32Table 5-2:32Figure 5-11:325.8 Using the RTCC Driver335.8.1 RTCC Function Interface335.8.1.1 rtcc_init33Figure 5-12:335.8.1.2 rtcc_handler33Figure 5-13:335.8.1.3 rtcc_set33Figure 5-14:345.8.1.4 time345.9 Using the MCP9800 Driver345.9.1 MCP9800 Function Interface345.9.1.1 mcp9800_init34Figure 5-15:345.9.1.2 mcp9800_get_temp34Figure 5-16:34Chapter 6. Troubleshooting356.1 Introduction356.2 Common Problems356.2.1 The board will not power up356.2.2 LCD is blank, but everything else works35Chapter 7. Schematics377.1 Introduction377.1.1 F1 LV Evaluation Platform Schematic (1 of 4)387.1.2 F1 LV Evaluation Platform Schematic (2 of 4)397.1.3 F1 LV Evaluation Platform Schematic (3 of 4)407.1.4 F1 LV Evaluation Platform Schematic (4 of 4)41Worldwide Sales44サイズ： 4.16MBページ数： 44Language: Englishマニュアルを開く
