データシート目次32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog11.0 Device Overview17FIGURE 1-1: PIC32MX330/350/370/430/450/470 Block Diagram17Table 1-1: Pinout I/O Descriptions182.0 Guidelines for Getting Started with 32-bit MCUs272.1 Basic Connection Requirements272.2 Decoupling Capacitors27FIGURE 2-1: Recommended Minimum Connection282.3 Capacitor on Internal Voltage Regulator (Vcap)282.4 Master Clear (MCLR) Pin28FIGURE 2-2: Example of MCLR Pin Connections282.5 ICSP Pins292.6 JTAG292.7 Trace292.8 External Oscillator Pins29FIGURE 2-3: Suggested Oscillator Circuit Placement292.9 Unused I/Os292.10 Sosc Design Recommendation30FIGURE 2-4: Recommended Oscillator Circuit Placement302.11 Typical Application Connection Examples31FIGURE 2-5: Capacitive Touch Sensing With Graphics Application31FIGURE 2-6: Audio Playback Application31FIGURE 2-7: Low-cost Controllerless (LCC) Graphics Application With Projected Capacitive Touch323.0 CPU333.1 Features33FIGURE 3-1: MIPS32® M4K® Processor Core Block Diagram333.2 Architecture Overview34Table 3-1: MIPS32® M4K® processor core High-Performance Integer Multiply/ Divide Unit Latencies and Repeat Rates34Table 3-2: Coprocessor 0 Registers35Table 3-3: MIPS32® M4K® processor core Exception Types363.3 Power Management363.4 EJTAG Debug Support364.0 Memory Organization374.1 Memory Layout37FIGURE 4-1: Memory Map for Devices with 64 KB of Program Memory38FIGURE 4-2: Memory Map for Devices With 128 KB of Program Memory39FIGURE 4-3: Memory Map for Devices With 256 KB of Program Memory40FIGURE 4-4: Memory Map for Devices With 512 KB of Program Memory414.2 Special Function Register Maps42TABLE 4-1: Bus Matrix Register Map42TABLE 4-2: Interrupt Register Map43TABLE 4-3: Timer1 THROUGH Timer5 Register Map45TABLE 4-4: Input Capture 1 THROUGH Input Capture 5 Register Map46TABLE 4-5: Output Compare 1 THROUGH Output Compare 5 Register Map47TABLE 4-6: I2C1 and I2C2 Register Map48TABLE 4-7: UART1 THROUGH UART5 Register Map49Table 4-8: spi2 and SPI2 Register Map51TABLE 4-9: ADC Register Map52TABLE 4-10: DMA Global Register Map54TABLE 4-11: DMA CRC Register Map54TABLE 4-12: DMA Channel 0 THROUGH Channel 3 Register Map55TABLE 4-13: Comparator Register Map58TABLE 4-14: Comparator Voltage Reference Register Map58TABLE 4-15: Flash Controller Register Map59TABLE 4-16: System Control Register Map60TABLE 4-17: DEVCFG: Device Configuration Word Summary61TABLE 4-18: Device and Revision ID Summary61TABLE 4-19: PORTA Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L devices Only62TABLE 4-20: PORTB Register Map63TABLE 4-21: PORTC Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512l, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only64TABLE 4-22: PORTC Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only65TABLE 4-23: PORTD Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only66TABLE 4-24: PORTD Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, PIC32MX470F512H Devices Only67TABLE 4-25: PORTE Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, PIC32MX470F512L Devices Only68TABLE 4-26: PORTE Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only69TABLE 4-27: PORTF Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, and PIC32MX370F512L Devices Only70TABLE 4-28: PORTF Register Map for PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only71TABLE 4-29: PORTF Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, and PIC32MX370F512H Devices Only72TABLE 4-30: PORTF Register Map for PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only73TABLE 4-31: PORTG Register Map for PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, and PIC32MX470F512L Devices Only74TABLE 4-32: PORTG Register Map for PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, and PIC32MX470F512H Devices Only75Table 4-33: Peripheral Pin Select Input Register Map76Table 4-34: Peripheral Pin Select Output Register Map78TABLE 4-35: Parallel Master Port Register Map82TABLE 4-36: Prefetch Register Map83TABLE 4-37: RTCC Register Map84TABLE 4-38: CTMU Register Map84TABLE 4-39: USB Register Map854.3 Control Registers88Register 4-1: BMXCON: Bus Matrix Configuration Register88Register 4-2: BMXDKPBA: Data RAM Kernel Program Base Address Register89Register 4-3: BMXDUDBA: Data RAM User Data Base Address Register90Register 4-4: BMXDUPBA: Data RAM User Program Base Address Register91Register 4-5: BMXDRMSZ: Data RAM Size Register92Register 4-6: BMXPUPBA: Program Flash (PFM) User Program Base Address Register92Register 4-7: BMXPFMSZ: Program Flash (PFM) Size Register93Register 4-8: BMXBOOTSZ: Boot Flash (IFM) Size Register935.0 Flash Program Memory955.1 Control Registers96Register 5-1: NVMCON: Programming Control Register96Register 5-2: NVMKEY: Programming Unlock Register97Register 5-3: NVMADDR: Flash Address Register97Register 5-4: NVMDATA: Flash Program Data Register98Register 5-5: NVMSRCADDR: Source Data Address Register986.0 Resets99FIGURE 6-1: System Reset Block Diagram996.1 Control Registers100Register 6-1: RCON: Reset Control Register100Register 6-2: RSWRST: Software Reset Register1017.0 Interrupt Controller103FIGURE 7-1: Interrupt Controller Module Block Diagram103Table 7-1: Interrupt IRQ, Vector and Bit Location1047.1 Interrupts Control Registers106Register 7-1: INTCON: Interrupt Control Register106Register 7-2: INTSTAT: Interrupt Status Register107Register 7-3: IPTMR: Interrupt Proximity Timer Register107Register 7-4: IFSx: Interrupt Flag Status Register108Register 7-5: IECx: Interrupt Enable Control Register108Register 7-6: IPCx: Interrupt Priority Control Register1098.0 Oscillator Configuration111FIGURE 8-1: PIC32MX330/350/370/430/450/470 Family Clock Diagram1128.1 Control Registers113Register 8-1: OSCCON: Oscillator Control Register113Register 8-2: OSCTUN: FRC Tuning Register116Register 8-3: REFOCON: Reference Oscillator Control Register117Register 8-4: REFOTRIM: Reference Oscillator Trim Register1199.0 Prefetch Cache1219.1 Features121FIGURE 9-1: Prefetch Cache Module Block Diagram1219.2 Control Registers122Register 9-1: CHECON: Cache Control Register122Register 9-2: CHEACC: Cache Access Register123Register 9-3: CHETAG: Cache TAG Register124Register 9-4: CHEMSK: Cache TAG Mask Register125Register 9-5: CHEW0: Cache Word 0125Register 9-6: CHEW1: Cache Word 1126Register 9-7: CHEW2: Cache Word 2126Register 9-8: CHEW3: Cache Word 3127Register 9-9: CHELRU: Cache LRU Register127Register 9-10: CHEHIT: Cache Hit Statistics Register128Register 9-11: CHEMIS: Cache Miss Statistics Register128Register 9-12: CHEPFABT: Prefetch Cache Abort Statistics Register12910.0 Direct Memory Access (DMA) Controller131FIGURE 10-1: DMA Block Diagram13110.1 Control Registers132Register 10-1: DMACON: DMA Controller Control Register132Register 10-2: DMASTAT: DMA Status Register133Register 10-3: DMAADDR: DMA Address Register133Register 10-4: DCRCCON: DMA CRC Control Register134Register 10-5: DCRCDATA: DMA CRC Data Register136Register 10-6: DCRCXOR: DMA CRCXOR Enable Register136Register 10-7: DCHxCON: DMA Channel ‘x’ Control Register137Register 10-8: DCHxECON: DMA Channel ‘x’ Event Control Register138Register 10-9: DCHxINT: DMA Channel ‘x’ Interrupt Control Register139Register 10-10: DCHxSSA: DMA Channel ‘x’ Source Start Address Register141Register 10-11: DCHxDSA: DMA Channel ‘x’ Destination Start Address Register141Register 10-12: DCHxSSIZ: DMA Channel ‘x’ Source Size Register142Register 10-13: DCHxDSIZ: DMA Channel ‘x’ Destination Size Register142Register 10-14: DCHxSPTR: DMA Channel ‘x’ Source Pointer Register143Register 10-15: DCHxDPTR: DMA Channel ‘x’ Destination Pointer Register143Register 10-16: DCHxCSIZ: DMA Channel ‘x’ Cell-Size Register144Register 10-17: DCHxCPTR: DMA Channel ‘x’ Cell Pointer Register144Register 10-18: DCHxDAT: DMA Channel ‘x’ Pattern Data Register14511.0 USB On-The-Go (OTG)147FIGURE 11-1: PIC32MX430/450/470 USB Interface Diagram14811.1 Control Registers149Register 11-1: U1OTGIR: USB OTG Interrupt Status Register149Register 11-2: U1OTGIE: USB OTG Interrupt Enable Register150Register 11-3: U1OTGSTAT: USB OTG Status Register151Register 11-4: U1OTGCON: USB OTG Control Register152Register 11-5: U1PWRC: USB Power Control Register153Register 11-6: U1IR: USB Interrupt Register154Register 11-7: U1IE: USB Interrupt Enable Register155Register 11-8: U1EIR: USB Error Interrupt Status Register156Register 11-9: U1EIE: USB Error Interrupt Enable Register158Register 11-10: U1STAT: USB Status Register159Register 11-11: U1CON: USB Control Register160Register 11-12: U1ADDR: USB Address Register162Register 11-13: U1FRML: USB Frame Number Low Register162Register 11-14: U1FRMH: USB Frame Number High Register163Register 11-15: U1TOK: USB Token Register163Register 11-16: U1SOF: USB SOF Threshold Register164Register 11-17: U1BDTP1: USB BDT Page 1 Register164Register 11-18: U1BDTP2: USB BDT PAGE 2 Register165Register 11-19: U1BDTP3: USB BDT PAGE 3 Register165Register 11-20: U1CNFG1: USB Configuration 1 Register166Register 11-21: U1EP0-U1EP15: USB Endpoint Control Register16712.0 I/O Ports169FIGURE 12-1: Block Diagram of a Typical Multiplexed Port Structure16912.1 Parallel I/O (PIO) Ports17012.2 CLR, SET, and INV Registers17012.3 Peripheral Pin Select171FIGURE 12-2: Remappable Input Example for U1RX171TABLE 12-1: Input Pin Selection172FIGURE 12-3: Example of Multiplexing of Remappable Output for RPA0174Table 12-2: Output Pin Selection17512.4 Control Registers177Register 12-1: [pin name]R: Peripheral Pin Select Input Register177Register 12-2: RPnR: Peripheral Pin Select Output Register177Register 12-3: CNCONx: Change Notice control for PORTx Register (x = A – G)17813.0 Timer117913.1 Additional Supported Features179FIGURE 13-1: Timer1 Block Diagram17913.2 Control Register180Register 13-1: T1CON: Type A Timer Control Register18014.0 Timer2/3, Timer4/518314.1 Additional Supported Features183FIGURE 14-1: Timer2, 3, 4, 5 Block Diagram (16-bit)183FIGURE 14-2: Timer2/3, 4/5 Block Diagram (32-bit)(1)18414.2 Control Register185Register 14-1: TxCON: Type B Timer Control Register18515.0 Input Capture187FIGURE 15-1: Input Capture Block Diagram18715.1 Control Register188Register 15-1: ICxCON: Input Capture ‘x’ Control Register18816.0 Output Compare191FIGURE 16-1: Output Compare Module Block Diagram19116.1 Control Register192Register 16-1: OCxCON: Output Compare ‘x’ Control Register19217.0 Serial Peripheral Interface (SPI)193FIGURE 17-1: SPI Module Block Diagram19317.1 Control Registers194Register 17-1: SPIx CON: SPI Control Register194Register 17-2: SPIxCON2: SPI Control Register 2197Register 17-3: SPIxSTAT: SPI Status Register19818.0 Inter-Integrated Circuit™ (I2C™)201FIGURE 18-1: I2C™ Block Diagram20218.1 Control Registers203Register 18-1: I2CxCON: I2C™ Control Register203Register 18-2: I2CxSTAT: I2C™ Status Register20519.0 Universal Asynchronous Receiver Transmitter (UART)207FIGURE 19-1: UART Simplified Block Diagram20719.1 Control Registers208Register 19-1: UxMODE: UARTx Mode Register208Register 19-2: UxSTA: UARTx Status and Control Register21019.2 Timing Diagrams212FIGURE 19-2: UART Reception212FIGURE 19-3: Transmission (8-bit or 9-bit Data)21220.0 Parallel Master Port (PMP)213FIGURE 20-1: PMP Module Pinout and Connections to External Devices21320.1 Control Registers214Register 20-1: PMCON: Parallel Port Control Register214Register 20-2: PMMODE: Parallel Port Mode Register216Register 20-3: PMADDR: Parallel Port Address Register218Register 20-4: PMAEN: Parallel Port Pin Enable Register219Register 20-5: PMSTAT: Parallel Port Status Register (Slave modes only)22021.0 Real-Time Clock and Calendar (RTCC)221FIGURE 21-1: RTCC Block Diagram22121.1 Control Registers222Register 21-1: RTCCON: RTC Control Register222Register 21-2: RTCALRM: RTC ALARM Control Register224Register 21-3: RTCTIME: RTC Time Value Register226Register 21-4: RTCDATE: RTC Date Value Register227Register 21-5: ALRMTIME: Alarm Time Value Register228Register 21-6: ALRMDATE: Alarm Date Value Register22922.0 10-bit Analog-to-Digital Converter (ADC)231FIGURE 22-1: ADC1 Module Block Diagram231FIGURE 22-2: ADC Conversion Clock Period Block Diagram23222.1 Control Registers233Register 22-1: AD1CON1: ADC Control Register 1233Register 22-2: AD1CON2: ADC Control Register 2235Register 22-3: AD1CON3: ADC Control Register 3236Register 22-4: AD1CHS: ADC Input Select Register237Register 22-5: AD1CSSL: ADC Input Scan Select Register23823.0 Comparator239FIGURE 23-1: Comparator Block Diagram23923.1 Control Registers240Register 23-1: CMxCON: Comparator Control Register240Register 23-2: CMSTAT: Comparator Status Register24124.0 Comparator Voltage Reference (CVref)243FIGURE 24-1: Comparator Voltage Reference Block Diagram24324.1 Control Register244Register 24-1: CVRCON: Comparator Voltage Reference Control Register24425.0 Charge Time Measurement Unit (CTMU)245FIGURE 25-1: CTMU Block Diagram24525.1 Control Register246Register 25-1: CTMUCON: CTMU Control Register24626.0 Power-Saving Features24926.1 Power Saving with CPU Running24926.2 CPU Halted Methods24926.3 Power-Saving Operation24926.4 Peripheral Module Disable251Table 26-1: Peripheral Module Disable Bits and Locations25127.0 Special Features25327.1 Configuration Bits253Register 27-1: DEVCFG0: Device Configuration Word 0253Register 27-2: DEVCFG1: Device Configuration Word 1255Register 27-3: DEVCFG2: Device Configuration Word 2257Register 27-4: DEVCFG3: Device Configuration Word 3259Register 27-5: CFGCON: Configuration Control Register260Register 27-6: DEVID: Device and Revision ID Register26127.2 Watchdog Timer (WDT)262Figure 27-1: Watchdog and Power-Up Timer Block Diagram262Register 27-7: WDTCON: Watchdog Timer Control Register26327.3 On-Chip Voltage Regulator264Figure 27-2: Connections for the On-Chip Regulator26427.4 Programming and Diagnostics264Figure 27-3: Block Diagram of Programming, Debugging and Trace Ports26428.0 Instruction Set26529.0 Development Support26729.1 MPLAB X Integrated Development Environment Software26729.2 MPLAB XC Compilers26829.3 MPASM Assembler26829.4 MPLINK Object Linker/ MPLIB Object Librarian26829.5 MPLAB Assembler, Linker and Librarian for Various Device Families26829.6 MPLAB X SIM Software Simulator26929.7 MPLAB REAL ICE In-Circuit Emulator System26929.8 MPLAB ICD 3 In-Circuit Debugger System26929.9 PICkit 3 In-Circuit Debugger/ Programmer26929.10 MPLAB PM3 Device Programmer26929.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits27029.12 Third-Party Development Tools27030.0 Electrical Characteristics27130.1 DC Characteristics272Table 30-1: Operating MIPS vs. Voltage272Table 30-2: Thermal Operating Conditions272Table 30-3: Thermal Packaging Characteristics272Table 30-4: DC Temperature and Voltage Specifications273Table 30-5: DC Characteristics: Operating Current (Idd)274Table 30-6: DC Characteristics: Idle Current (Iidle)275Table 30-7: DC Characteristics: Power-Down Current (Ipd)276Table 30-8: DC Characteristics: I/O Pin Input Specifications277TABLE 30-9: DC Characteristics: I/O Pin Output Specifications280Table 30-10: Electrical Characteristics: BOR281Table 30-11: Electrical Characteristics: HVD281Table 30-12: DC Characteristics: Program Memory282Table 30-13: DC Characteristics: Program Flash Memory Wait State282Table 30-14: Comparator Specifications283Table 30-15: Internal Voltage Regulator Specifications28330.2 AC Characteristics and Timing Parameters284Figure 30-1: Load Conditions for Device Timing Specifications284Table 30-16: Capacitive Loading Requirements on Output Pins284Figure 30-2: External Clock Timing284Table 30-17: External Clock Timing Requirements285Table 30-18: PLL Clock Timing Specifications286Table 30-19: Internal FRC Accuracy286Table 30-20: Internal LPRC Accuracy286Figure 30-3: I/O Timing Characteristics287Table 30-21: I/O Timing Requirements287Figure 30-4: Power-On Reset Timing Characteristics288Figure 30-5: External Reset Timing Characteristics289Table 30-22: Resets Timing289Figure 30-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics290Table 30-23: Timer1 External Clock Timing Requirements(1)290Table 30-24: Timer2, 3, 4, 5 External Clock Timing Requirements291Figure 30-7: Input Capture (CAPx) Timing Characteristics291Table 30-25: Input Capture Module Timing Requirements291Figure 30-8: Output Compare Module (OCx) Timing Characteristics292Table 30-26: Output Compare Module Timing Requirements292Figure 30-9: OCx/PWM Module Timing Characteristics292Table 30-27: Simple OCx/PWM Mode Timing Requirements292Figure 30-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics293Table 30-28: SPIx Master Mode (CKE = 0) Timing Requirements293Figure 30-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics294Table 30-29: SPIx Module Master Mode (CKE = 1) Timing Requirements294Figure 30-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics295Table 30-30: SPIx Module Slave Mode (CKE = 0) Timing Requirements295Figure 30-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics296Table 30-31: SPIx Module Slave Mode (CKE = 1) Timing Requirements296Figure 30-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)298Figure 30-15: I2Cx Bus Data Timing Characteristics (Master Mode)298Table 30-32: I2Cx Bus Data Timing Requirements (Master Mode)299Figure 30-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)301Figure 30-17: I2Cx Bus Data Timing Characteristics (Slave Mode)301Table 30-33: I2Cx Bus Data Timing Requirements (Slave Mode)302Table 30-34: ADC Module Specifications304Table 30-35: 10-bit Conversion Rate Parameters306Table 30-36: Analog-to-Digital Conversion Timing Requirements307Figure 30-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000)308Figure 30-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)309Figure 30-20: Parallel Slave Port Timing310Table 30-37: Parallel Slave Port Requirements310Figure 30-21: Parallel Master Port Read Timing Diagram311Table 30-38: Parallel Master Port Read Timing Requirements311Figure 30-22: Parallel Master Port Write Timing Diagram312Table 30-39: Parallel Master Port Write Timing Requirements312Table 30-40: OTG Electrical Specifications313TABLE 30-41: CTMU Current Source Specifications314Figure 30-23: EJTAG Timing Characteristics315Table 30-42: EJTAG Timing Requirements31531.0 DC and AC Device Characteristics Graphs317FIGURE 31-1: Voh – 4x Driver Pins317FIGURE 31-2: Voh – 8x Driver Pins317FIGURE 31-3: Vol – 4x Driver Pins317FIGURE 31-4: Vol – 8x Driver Pins317FIGURE 31-5: Typical Ipd Current @ Vdd = 3.3V318FIGURE 31-6: Typical Ipd Current @ Vdd = 3.3V318FIGURE 31-7: Typical Ipd Current @ Vdd = 3.3V318FIGURE 31-8: Typical Iidle Current @ Vdd = 3.3V318FIGURE 31-9: Typical Iidle Current @ Vdd = 3.3V319FIGURE 31-10: Typical Iidle Current @ Vdd = 3.3V319FIGURE 31-11: Typical Idd Current @ Vdd = 3.3V319FIGURE 31-12: Typical Idd Current @ Vdd = 3.3V319FIGURE 31-13: Typical Idd Current @ Vdd = 3.3V320FIGURE 31-14: Typical FRC Frequency @ Vdd = 3.3V320FIGURE 31-15: Typical LPRC Frequency @ Vdd = 3.3V320FIGURE 31-16: Typical CTMU Temperature DIODE Forward Voltage32032.0 Packaging Information32132.1 Package Marking Information32132.1 Package Marking Information (Continued)32232.2 Package Details323Appendix A: Revision History335TABLE A-1: Major Section Updates335TABLE A-2: Major Section Updates336INDEX337The Microchip Web Site341Customer Change Notification Service341Customer Support341Worldwide Sales and Service344サイズ： 11.8MBページ数： 344Language: Englishマニュアルを開く
