データシート目次High-Performance RISC CPU:3Flexible Oscillator Structure:3Analog Features:3Extreme Low-Power Management PIC18(L)F2X/4XK22 with XLP:3Special Microcontroller Features:3Peripheral Highlights:3Pin Diagrams (28-pin)5Pin Diagrams (40-pin)6Pin Diagrams (44-pin)7Table of Contents11Most Current Data Sheet12Errata12Customer Notification System121.0 Device Overview131.1 New Core Features131.1.1 XLP Technology131.1.2 Multiple Oscillator Options and Features131.2 Other Special Features141.3 Details on Individual Family Members14TABLE 1-1: Device Features15FIGURE 1-1: PIC18(L)F2X/4XK22 Family Block Diagram16TABLE 1-2: PIC18(L)F2XK22 Pinout I/O Descriptions17TABLE 1-3: PIC18(L)F4XK22 Pinout I/O Descriptions212.0 Oscillator Module (With Fail-Safe Clock Monitor)272.1 Overview27FIGURE 2-1: Simplified OSCILLATOR SYSTEM BLOCK DIAGRAM282.2 Oscillator Control292.2.1 Main System Clock Selection292.2.2 Internal Frequency Selection292.2.3 Low Frequency Selection292.2.4 Power Management29FIGURE 2-2: Internal Oscillator Mux Block Diagram30FIGURE 2-3: PLL_Select Block Diagram30TABLE 2-1: PLL_Select Truth Table30FIGURE 2-4: Secondary Oscillator and External Clock Inputs312.3 Register Definitions: Oscillator Control32Register 2-1: OSCCON: Oscillator Control Register32Register 2-2: OSCCON2: Oscillator Control Register 2332.4 Clock Source Modes342.5 External Clock Modes342.5.1 Oscillator Start-up Timer (OST)34TABLE 2-2: Oscillator Delay Examples342.5.2 EC Mode34FIGURE 2-5: External Clock (EC) Mode Operation342.5.3 LP, XT, HS Modes35FIGURE 2-6: Quartz Crystal Operation (LP, XT or HS Mode)35FIGURE 2-7: Ceramic Resonator Operation (XT or HS Mode)352.5.4 External RC Modes36FIGURE 2-8: External RC Modes362.6 Internal Clock Modes362.6.1 INTOSC with I/O or Clockout362.7 Register Definitions: Oscillator Tuning37Register 2-3: OSCTUNE: Oscillator Tuning ReGister372.7.1 LFINTOSC382.7.2 Frequency Select Bits (IRCF)382.7.3 INTOSC Frequency Drift382.8 PLL Frequency Multiplier392.8.1 PLL in External Oscillator Modes392.8.2 PLL in HFINTOSC Modes392.9 Effects of Power-Managed Modes on the Various Clock Sources402.10 Power-up Delays40TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode412.11 Clock Switching412.11.1 System Clock Select (SCS<1:0>) Bits412.11.2 Oscillator Start-up Time-out Status (OSTS) Bit412.11.3 Clock Switch Timing422.12 Two-Speed Clock Start-up Mode422.12.1 Two-Speed Start-up Mode Configuration422.12.2 Two-Speed Start-up Sequence432.12.3 Checking Two-Speed Clock Status43FIGURE 2-9: Clock Switch Timing432.13 Fail-Safe Clock Monitor44FIGURE 2-10: FSCM Block Diagram442.13.1 Fail-Safe Detection442.13.2 Fail-Safe Operation442.13.3 Fail-Safe Condition Clearing442.13.4 Reset or Wake-up from Sleep44FIGURE 2-11: FSCM Timing Diagram45TABLE 2-4: Registers Associated with Clock Sources45TABLE 2-5: Configuration Registers Associated with Clock Sources453.0 Power-Managed Modes473.1 Selecting Power-Managed Modes473.1.1 Clock Sources473.1.2 Entering Power-Managed Modes47TABLE 3-1: Power-Managed Modes473.1.3 Multiple Functions of the Sleep Command483.2 Run Modes483.2.1 PRI_RUN Mode483.2.2 SEC_RUN Mode483.2.3 RC_RUN Mode48FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode49FIGURE 3-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)49TABLE 3-2: Internal Oscillator Frequency Stability Bits50FIGURE 3-3: Transition Timing From RC_RUN Mode to PRI_RUN Mode503.3 Sleep Mode513.4 Idle Modes51FIGURE 3-4: Transition Timing for Entry to Sleep Mode51FIGURE 3-5: Transition Timing for Wake from Sleep (HSPLL)523.4.1 PRI_IDLE Mode523.4.2 SEC_IDLE Mode52FIGURE 3-6: Transition Timing for Entry to Idle Mode52FIGURE 3-7: Transition Timing for Wake from Idle to Run Mode533.4.3 RC_IDLE Mode533.5 Exiting Idle and Sleep Modes543.5.1 Exit by Interrupt543.5.2 Exit by WDT Time-out543.5.3 Exit by Reset543.5.4 Exit without an Oscillator Start-up Delay543.6 Selective Peripheral Module Control553.7 Register Definitions: Peripheral Module Disable55Register 3-1: PMD0: Peripheral Module Disable Register 055Register 3-2: PMD1: Peripheral Module Disable Register 156Register 3-3: PMD2: Peripheral Module Disable Register 2574.0 Reset594.1 RCON Register59FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit594.2 Register Definitions: Reset Control60Register 4-1: RCON: RESET Control Register604.3 Master Clear (MCLR)614.4 Power-on Reset (POR)61FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)614.5 Brown-out Reset (BOR)624.5.1 Detecting BOR624.5.2 Software Enabled BOR624.5.3 Disabling BOR in Sleep Mode624.5.4 Minimum BOR Enable Time62TABLE 4-1: BOR Configurations634.6 Device Reset Timers634.6.1 Power-up Timer (PWRT)634.6.2 Oscillator Start-up Timer (OST)634.6.3 PLL Lock Time-out634.6.4 Time-out Sequence63TABLE 4-2: Time-out in Various Situations64FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)64FIGURE 4-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 164FIGURE 4-5: Time-out Sequence on Power-up (Mclr not Tied to Vdd): Case 265FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)65FIGURE 4-7: Time-out Sequence on Por w/PLL Enabled (MCLR Tied to Vdd)664.7 Reset State of Registers67TABLE 4-3: Status Bits, their Significance and the Initialization Condition for RCON Register67TABLE 4-4: Registers Associated with Resets67TABLE 4-5: Configuration Registers Associated with Resets685.0 Memory Organization695.1 Program Memory Organization69FIGURE 5-1: Program Memory Map and Stack for PIC18(L)F2X/4XK22 Devices705.1.1 Program Counter705.1.2 Return Address Stack70FIGURE 5-2: Return Address Stack and Associated Registers715.2 Register Definitions: Stack Pointer72Register 5-1: STKPTR: Stack Pointer Register725.2.1 Fast Register Stack72EXAMPLE 5-1: Fast Register Stack Code Example735.2.2 Look-up Tables in Program Memory73EXAMPLE 5-2: Computed GOTO Using an Offset Value735.3 PIC18 Instruction Cycle745.3.1 Clocking Scheme745.3.2 Instruction Flow/Pipelining74FIGURE 5-3: Clock/ Instruction Cycle74EXAMPLE 5-3: Instruction Pipeline Flow745.3.3 Instructions in Program Memory75FIGURE 5-4: Instructions in Program Memory755.3.4 Two-Word Instructions75EXAMPLE 5-4: Two-Word Instructions755.4 Data Memory Organization765.4.1 Bank Select Register (BSR)76FIGURE 5-5: Data Memory Map for PIC18(L)F23K22 and PIC18(L)F43K22 Devices77FIGURE 5-6: Data Memory Map for PIC18(L)F24K22 and PIC18(L)F44K22 Devices78FIGURE 5-7: Data Memory Map for PIC18(L)F25K22 and PIC18(L)F45K22 Devices79FIGURE 5-8: Data Memory Map for PIC18(L)F26K22 and PIC18(L)F46K22 Devices80FIGURE 5-9: Use of the Bank Select Register (Direct Addressing)815.4.2 Access Bank825.4.3 General Purpose Register File825.4.4 Special Function Registers82TABLE 5-1: Special Function Register Map for PIC18(L)F2X/4XK22 Devices83TABLE 5-2: Register File Summary for PIC18(L)F2X/4XK22 Devices845.4.5 Status Register895.5 Register Definitions: Status89Register 5-2: STATUS: STATUS Register895.6 Data Addressing Modes905.6.1 Inherent and Literal Addressing905.6.2 Direct Addressing905.6.3 Indirect Addressing90EXAMPLE 5-5: How to Clear Ram (Bank 1) Using Indirect Addressing90FIGURE 5-10: Indirect Addressing915.7 Data Memory and the Extended Instruction Set925.7.1 Indexed Addressing with Literal Offset925.7.2 Instructions Affected by Indexed Literal Offset Mode92FIGURE 5-11: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)935.7.3 Mapping the Access Bank in Indexed Literal Offset Mode945.8 PIC18 Instruction Execution and the Extended Instruction Set94FIGURE 5-12: Remapping the Access Bank with Indexed Literal Offset Addressing946.0 Flash Program Memory956.1 Table Reads and Table Writes95FIGURE 6-1: Table Read Operation95FIGURE 6-2: Table Write Operation966.2 Control Registers966.2.1 EECON1 and EECON2 Registers966.3 Register Definitions: Memory Control97Register 6-1: EECON1: Data EEPROM Control 1 Register976.3.1 TABLAT – Table Latch Register986.3.2 TBLPTR – Table Pointer Register986.3.3 Table Pointer Boundaries98TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions98FIGURE 6-3: Table Pointer Boundaries Based on Operation986.4 Reading the Flash Program Memory99FIGURE 6-4: Reads from Flash Program Memory99EXAMPLE 6-1: Reading a Flash Program Memory Word996.5 Erasing Flash Program Memory1006.5.1 Flash Program Memory Erase Sequence100EXAMPLE 6-2: Erasing a Flash Program Memory block1006.6 Writing to Flash Program Memory101FIGURE 6-5: Table Writes to Flash Program Memory1016.6.1 Flash Program Memory Write Sequence101EXAMPLE 6-3: Writing to Flash Program Memory102EXAMPLE 6-3: Writing to Flash Program Memory (Continued)1036.6.2 Write Verify1036.6.3 Unexpected Termination of Write Operation1036.6.4 Protection Against Spurious Writes1036.7 Flash Program Operation During Code Protection103TABLE 6-2: Registers Associated with Program Flash Memory1037.0 Data EEPROM Memory1057.1 EEADR and EEADRH Registers1057.2 EECON1 and EECON2 Registers105Register 7-1: EECON1: Data EEPROM Control 1 Register1067.3 Reading the Data EEPROM Memory1077.4 Writing to the Data EEPROM Memory1077.5 Write Verify107EXAMPLE 7-1: Data EEPROM Read107EXAMPLE 7-2: Data EEPROM Write1077.6 Operation During Code-Protect1087.7 Protection Against Spurious Write1087.8 Using the Data EEPROM108EXAMPLE 7-3: Data EEPROM Refresh Routine108TABLE 7-1: Registers Associated with Data EEPROM Memory1098.0 8 X 8 Hardware Multiplier1118.1 Introduction1118.2 Operation111EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine111EXAMPLE 8-2: 8 x 8 Signed Multiply Routine111TABLE 8-1: Performance Comparison for Various Multiply Operations111EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm112EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine112EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm112EXAMPLE 8-4: 16 x 16 Signed Multiply Routine1129.0 Interrupts1139.1 Mid-Range Compatibility1139.2 Interrupt Priority1139.3 Interrupt Response113FIGURE 9-1: PIC18 Interrupt Logic1149.4 INTCON Registers1159.5 PIR Registers1159.6 PIE Registers1159.7 IPR Registers1159.8 Register Definitions: Interrupt Control116Register 9-1: INTCON: Interrupt Control Register116Register 9-2: INTCON2: Interrupt Control 2 Register117Register 9-3: INTCON3: Interrupt Control 3 Register118Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1119Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2120Register 9-6: PIR3: Peripheral Interrupt (Flag) Register 3121Register 9-7: PIR4: Peripheral Interrupt (Flag) Register 4122Register 9-8: PIR5: Peripheral Interrupt (Flag) Register 5123Register 9-9: PIE1: Peripheral Interrupt Enable (Flag) Register 1124Register 9-10: PIE2: Peripheral Interrupt Enable (Flag) Register 2125Register 9-11: PIE3: Peripheral Interrupt Enable (Flag) Register 3126Register 9-12: PIE4: Peripheral Interrupt Enable (Flag) Register 4127Register 9-13: PIE5: Peripheral Interrupt Enable (Flag) Register 5127Register 9-14: IPR1: Peripheral Interrupt Priority Register 1128Register 9-15: IPR2: Peripheral Interrupt Priority Register 2129Register 9-16: IPR3: Peripheral Interrupt Priority Register 3130Register 9-17: IPR4: Peripheral Interrupt Priority Register 4131Register 9-18: IPR5: Peripheral Interrupt Priority Register 51319.9 INTn Pin Interrupts1329.10 TMR0 Interrupt1329.11 PORTB Interrupt-on-Change1329.12 Context Saving During Interrupts132EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM132TABLE 9-1: Registers Associated with Interrupts133TABLE 9-2: Configuration Registers Associated with Interrupts13310.0 I/O Ports135FIGURE 10-1: Generic I/O Port Operation13510.1 PORTA Registers135EXAMPLE 10-1: Initializing PORTA135TABLE 10-1: PORTA I/O Summary136TABLE 10-2: Registers Associated with PORTA137TABLE 10-3: Configuration Registers Associated with PORTA13710.1.1 PORTA Output Priority138TABLE 10-4: Port Pin Function Priority13810.2 PORTB Registers140EXAMPLE 10-2: Initializing PORTB14010.2.1 PORTB Output Priority14010.3 Additional PORTB Pin Functions14010.3.1 Weak Pull-Ups14010.3.2 Interrupt-On-Change14010.3.3 Alternate Functions141TABLE 10-5: PORTB I/O Summary141TABLE 10-6: Registers Associated with PORTB143TABLE 10-7: Configuration Registers Associated with PORTB14410.4 PORTC Registers144EXAMPLE 10-3: Initializing PORTC14410.4.1 PORTC Output Priority144TABLE 10-8: PORTC I/O Summary145TABLE 10-9: Registers Associated with PORTC147TABLE 10-10: Configuration Registers Associated with PORTC14710.5 PORTD Registers148EXAMPLE 10-4: Initializing PORTD14810.5.1 PORTD Output Priority148TABLE 10-11: PORTD I/O Summary149TABLE 10-12: Registers Associated with PORTD150TABLE 10-13: Configuration Registers Associated with PORTD15010.6 PORTE Registers15110.6.1 PORTE on 40/44-Pin Devices151EXAMPLE 10-5: Initializing PORTE15110.6.2 PORTE on 28-Pin Devices15110.6.3 RE3 Weak Pull-Up15110.6.4 PORTE Output Priority151TABLE 10-14: PORTE I/O Summary152TABLE 10-15: Registers Associated with PORTE152TABLE 10-16: Configuration Registers Associated with PORTE15310.7 Port Analog Control15310.8 Port Slew Rate Control15310.9 Register Definitions – Port Control153Register 10-1: PORTx(1): PORTx Register153Register 10-2: PORTE: PORTE Register154Register 10-3: ANSELA – PORTA Analog Select Register154Register 10-4: ANSELB – PORTB Analog Select Register155Register 10-5: ANSELC – PORTC Analog Select Register155Register 10-6: ANSELD – PORTD Analog Select Register155Register 10-7: ANSELE – PORTE Analog Select Register156Register 10-8: TRISx: PORTx Tri-State Register(1)156Register 10-9: TRISE: PORTE Tri-State Register156Register 10-10: LATx: Portx Output Latch Register(1)157Register 10-11: LATE: PORTE Output Latch Register(1)157Register 10-12: WPUB: Weak Pull-up PORTB Register157Register 10-13: IOCB: Interrupt-on-Change PORTB Control register158Register 10-14: SLRCON: Slew Rate Control Register15811.0 Timer0 Module15911.1 Register Definitions: Timer0 Control159Register 11-1: T0CON: Timer0 Control Register15911.2 Timer0 Operation16011.3 Timer0 Reads and Writes in 16-Bit Mode160FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)160FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)16111.4 Prescaler16111.4.1 Switching Prescaler Assignment16111.5 Timer0 Interrupt161TABLE 11-1: Registers Associated with Timer016112.0 Timer1/3/5 Module with Gate Control163FIGURE 12-1: Timer1/3/5 Block Diagram16312.1 Timer1/3/5 Operation164TABLE 12-1: Timer1/3/5 Enable Selections16412.2 Clock Source Selection16412.2.1 Internal Clock Source16412.2.2 External Clock Source164TABLE 12-2: Clock Source Selections16412.3 Timer1/3/5 Prescaler16512.4 Secondary Oscillator16512.5 Timer1/3/5 Operation in Asynchronous Counter Mode16512.5.1 Reading and Writing Timer1/3/5 in Asynchronous Counter Mode16512.6 Timer1/3/5 16-Bit Read/Write Mode165FIGURE 12-2: Timer1/3/5 16-Bit Read/Write Mode Block Diagram16612.7 Timer1/3/5 Gate16612.7.1 Timer1/3/5 Gate Enable166TABLE 12-3: Timer1/3/5 Gate Enable Selections16612.7.2 Timer1/3/5 Gate Source Selection166TABLE 12-4: Timer1/3/5 Gate Sources166TABLE 12-5: Gate Resources for Timer2/4/6 Match to PR2/4/616612.7.3 Timer1/3/5 Gate Toggle Mode16712.7.4 Timer1/3/5 Gate Single-Pulse Mode16712.7.5 Timer1/3/5 Gate Value Status16712.7.6 Timer1/3/5 Gate Event Interrupt16712.8 Timer1/3/5 Interrupt16812.9 Timer1/3/5 Operation During Sleep16812.10 ECCP/CCP Capture/Compare Time Base16812.11 ECCP/CCP Special Event Trigger168FIGURE 12-3: Timer1/3/5 Incrementing Edge169FIGURE 12-4: Timer1/3/5 Gate Enable Mode169FIGURE 12-5: Timer1/3/5 Gate Toggle Mode170FIGURE 12-6: Timer1/3/5 Gate Single-Pulse Mode170FIGURE 12-7: Timer1/3/5 Gate Single-Pulse and Toggle Combined Mode17112.12 Peripheral Module Disable17112.13 Register Definitions: Timer1/3/5 Control172Register 12-1: TxCON: Timer1/3/5 Control Register172Register 12-2: TxGCON: Timer1/3/5 Gate Control Register173TABLE 12-6: Registers Associated with Timer1/3/5 as a Timer/Counter174TABLE 12-7: Configuration Registers Associated with Timer1/3/517413.0 Timer2/4/6 Module175FIGURE 13-1: Timer2/4/6 Block Diagram17513.1 Timer2/4/6 Operation17613.2 Timer2/4/6 Interrupt17613.3 Timer2/4/6 Output17613.4 Timer2/4/6 Operation During Sleep17613.5 Peripheral Module Disable17613.6 Register Definitions: Timer2/4/6 Control177Register 13-1: TxCON: Timer2/Timer4/Timer6 Control Register177TABLE 13-1: Summary of Registers Associated With Timer2/4/617814.0 Capture/Compare/PWM Modules179TABLE 14-1: PWM Resources17914.1 Capture Mode180FIGURE 14-1: Capture Mode Operation Block Diagram18014.1.1 CCP pin Configuration180TABLE 14-2: CCP Pin Multiplexing18014.1.2 Timer1 Mode Resource18014.1.3 Software Interrupt Mode18014.1.4 CCP Prescaler181EXAMPLE 14-1: Changing Between Capture Prescalers18114.1.5 Capture During Sleep181TABLE 14-3: Registers Associated with Capture181TABLE 14-4: Configuration Registers Associated with Capture18214.2 Compare Mode183FIGURE 14-2: Compare Mode Operation Block Diagram18314.2.1 CCP Pin Configuration18314.2.2 Timerx Mode Resource18314.2.3 Software Interrupt Mode18314.2.4 Special Event Trigger18414.2.5 Compare During Sleep184TABLE 14-5: Registers Associated with Compare184TABLE 14-6: Configuration Registers Associated with Compare18514.3 PWM Overview18614.3.1 Standard PWM Operation186FIGURE 14-3: CCP PWM Output Signal186FIGURE 14-4: Simplified PWM Block Diagram18614.3.2 Setup for PWM Operation18614.3.3 PWM Timer Resource18714.3.4 PWM Period187EQUATION 14-1: PWM Period18714.3.5 PWM Duty Cycle187EQUATION 14-2: Pulse Width187EQUATION 14-3: Duty Cycle Ratio18714.3.6 PWM Resolution188EQUATION 14-4: PWM Resolution188TABLE 14-7: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)188TABLE 14-8: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)188TABLE 14-9: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)18814.3.7 Operation in Sleep Mode18814.3.8 Changes in System Clock Frequency18814.3.9 Effects of Reset188TABLE 14-10: Registers Associated with Standard PWM189TABLE 14-11: Configuration Registers Associated with Standard PWM18914.4 PWM (Enhanced Mode)190FIGURE 14-5: Example Simplified Block Diagram of the Enhanced PWM Mode190TABLE 14-12: Example Pin Assignments for Various PWM Enhanced Modes191FIGURE 14-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)191FIGURE 14-7: Example Enhanced PWM Output Relationships (Active-Low State)19214.4.1 Half-Bridge Mode193FIGURE 14-8: Example of Half- Bridge PWM Output193FIGURE 14-9: Example of Half-Bridge Applications19314.4.2 Full-Bridge Mode194FIGURE 14-10: Example of Full-Bridge Application194FIGURE 14-11: Example of Full-Bridge PWM Output195FIGURE 14-12: Example of PWM Direction Change196FIGURE 14-13: Example of PWM Direction Change at Near 100% Duty Cycle19714.4.3 Enhanced PWM Auto- shutdown Mode197FIGURE 14-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)19814.4.4 Auto-Restart Mode198FIGURE 14-15: PWM Auto-shutdown With Auto-Restart (PxRSEN = 1)19814.4.5 Programmable Dead-Band Delay Mode199FIGURE 14-16: Example of Half- Bridge PWM Output199FIGURE 14-17: Example of Half-Bridge Applications19914.4.6 PWM Steering Mode200FIGURE 14-18: Simplified Steering Block Diagram20014.4.7 Start-up Considerations201FIGURE 14-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)201FIGURE 14-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)20114.4.8 SETUP FOR ECCP PWM OPERATION using ECCP1 and Timer2202TABLE 14-13: Registers Associated with Enhanced PWM203TABLE 14-14: Configuration Registers Associated with Enhanced PWM20414.5 Register Definitions: ECCP Control205Register 14-1: CCPXCON: Standard CCPx Control Register205Register 14-2: CCPxCON: Enhanced CCPx Control Register206Register 14-3: CCPTMRS0: PWM Timer Selection Control Register 0208Register 14-4: CCPTMRS1: PWM Timer Selection Control Register 1208Register 14-5: ECCPxAS: CCPx Auto-Shutdown Control Register209Register 14-6: PWMxCON: Enhanced PWM Control Register210Register 14-7: PSTRxCON: PWM Steering Control Register(1)21015.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module21115.1 Master SSPx (MSSPx) Module Overview211FIGURE 15-1: MSSPx Block Diagram (SPI mode)211FIGURE 15-2: MSSPx Block Diagram (I2C™ Master mode)212FIGURE 15-3: MSSPx Block Diagram (I2C™ Slave mode)21315.2 SPI Mode Overview214FIGURE 15-4: SPI Master and Multiple Slave Connection21515.2.1 SPI Mode Registers21515.2.2 SPI Mode Operation215FIGURE 15-5: SPI Master/Slave Connection21615.2.3 SPI Master Mode217FIGURE 15-6: SPI Mode Waveform (Master Mode)21715.2.4 SPI Slave Mode21815.2.5 Slave Select Synchronization218FIGURE 15-7: SPI Daisy-Chain Connection219FIGURE 15-8: Slave Select Synchronous Waveform219FIGURE 15-9: SPI Mode Waveform (Slave Mode With CKE = 0)220FIGURE 15-10: SPI Mode Waveform (SLAve Mode With CKE = 1)22015.2.6 SPI Operation IN Sleep Mode221TABLE 15-1: Registers Associated with SPI Operation22115.3 I2C Mode Overview222FIGURE 15-11: I2C™ Master/ Slave Connection22215.3.1 Clock Stretching22315.3.2 Arbitration22315.4 I2C Mode Operation22415.4.1 Byte Format22415.4.2 Definition of I2C Terminology22415.4.3 SDAx and SCLx Pins22415.4.4 SDAx Hold Time224TABLE 15-2: I2C™ Bus Terms22415.4.5 Start Condition22515.4.6 STOP Condition22515.4.7 Restart Condition22515.4.8 START/STOP Condition Interrupt Masking225FIGURE 15-12: I2C™ Start and Stop Conditions225FIGURE 15-13: I2C™ Restart Condition22515.4.9 Acknowledge Sequence22615.5 I2C Slave Mode Operation22615.5.1 Slave Mode Addresses22615.5.2 Slave Reception227FIGURE 15-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)228FIGURE 15-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)229FIGURE 15-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)230FIGURE 15-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)23115.5.3 SLAVE Transmission232FIGURE 15-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)233FIGURE 15-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)23515.5.4 Slave Mode 10-bit Address Reception23615.5.5 10-bit Addressing With Address Or Data Hold236FIGURE 15-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)237FIGURE 15-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)238FIGURE 15-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)23915.5.6 Clock Stretching24015.5.7 Clock Synchronization and the CKP bit240FIGURE 15-23: Clock Synchronization Timing24015.5.8 General Call Address Support241FIGURE 15-24: Slave Mode General Call Address Sequence24115.5.9 SSPx Mask Register24115.6 I2C Master Mode24215.6.1 I2C Master Mode Operation24215.6.2 Clock Arbitration243FIGURE 15-25: Baud Rate Generator Timing with Clock Arbitration24315.6.3 WCOL Status Flag24315.6.4 I2C Master Mode Start Condition Timing244FIGURE 15-26: First Start Bit Timing24415.6.5 I2C Master Mode Repeated Start Condition Timing245FIGURE 15-27: Repeat Start Condition Waveform24515.6.6 I2C Master Mode Transmission246FIGURE 15-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)24715.6.7 I2C Master Mode Reception248FIGURE 15-29: I2C™ Master Mode Waveform (Reception, 7-Bit Address)24915.6.8 Acknowledge Sequence Timing25015.6.9 Stop Condition Timing250FIGURE 15-30: Acknowledge Sequence Waveform250FIGURE 15-31: Stop Condition Receive or Transmit Mode25115.6.10 Sleep Operation25115.6.11 Effects of a Reset25115.6.12 Multi-Master Mode25115.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration252FIGURE 15-32: Bus Collision Timing for Transmit and Acknowledge252FIGURE 15-33: Bus Collision During Start Condition (SDAx Only)253FIGURE 15-34: Bus Collision During Start Condition (SCLx = 0)254FIGURE 15-35: BRG Reset Due to Sda Arbitration During Start Condition254FIGURE 15-36: Bus Collision During a Repeated Start Condition (Case 1)255FIGURE 15-37: Bus Collision During Repeated Start Condition (Case 2)255FIGURE 15-38: Bus Collision During a Stop Condition (Case 1)256FIGURE 15-39: Bus Collision During a Stop Condition (Case 2)256TABLE 15-3: Registers Associated with I2C™ Operation25715.7 Baud Rate Generator258EQUATION 15-1:258FIGURE 15-40: Baud Rate Generator Block Diagram258TABLE 15-4: MSSPx Clock Rate w/BRG25815.8 Register Definitions: MSSP Control259Register 15-1: SSPxSTAT: SSPx STATUS Register259Register 15-2: SSPxCON1: SSPx Control Register 1260Register 15-3: SSPxCON2: SSPx Control Register 2262Register 15-4: SSPxCON3: SSPx Control Register 3263Register 15-5: SSPxMSK: SSPx Mask Register264Register 15-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode)26516.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)267FIGURE 16-1: EUSART Transmit Block Diagram267FIGURE 16-2: EUSART Receive Block Diagram26816.1 EUSART Asynchronous Mode26916.1.1 EUSART Asynchronous Transmitter269FIGURE 16-3: Asynchronous Transmission270FIGURE 16-4: Asynchronous Transmission (Back-to-Back)271TABLE 16-1: Registers Associated with Asynchronous Transmission27116.1.2 EUSART Asynchronous Receiver272FIGURE 16-5: Asynchronous Reception275TABLE 16-2: Registers Associated with Asynchronous Reception27516.2 Clock Accuracy with Asynchronous Operation27616.3 Register Definitions: EUSART Control277Register 16-1: TXSTAx: Transmit Status AND Control REGISTER277Register 16-2: RCSTAx: Receive Status and Control Register278Register 16-3: BAUDCONx: Baud Rate Control Register27916.4 EUSART Baud Rate Generator (BRG)280EXAMPLE 16-1: Calculating Baud Rate Error280TABLE 16-3: Baud Rate Formulas280TABLE 16-4: Registers Associated with Baud Rate Generator281TABLE 16-5: BAUD Rates for Asynchronous Modes28116.4.1 Auto-Baud Detect284TABLE 16-6: BRG Counter Clock Rates284FIGURE 16-6: Automatic Baud Rate Calibration28416.4.2 Auto-baud Overflow28516.4.3 Auto-Wake-up on Break285FIGURE 16-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation286FIGURE 16-8: Auto-Wake-up Bit (WUE) Timings During Sleep28616.4.4 BREAK Character Sequence28716.4.5 Receiving a BREAK Character287FIGURE 16-9: Send Break Character Sequence28716.5 EUSART Synchronous Mode28816.5.1 Synchronous Master Mode288FIGURE 16-10: Synchronous Transmission289FIGURE 16-11: Synchronous Transmission (Through TXEN)289TABLE 16-7: Registers Associated with Synchronous Master Transmission290FIGURE 16-12: Synchronous Reception (Master Mode, SREN)292TABLE 16-8: Registers Associated with Synchronous Master Reception29216.5.2 Synchronous Slave Mode293TABLE 16-9: Registers Associated with Synchronous Slave Transmission294TABLE 16-10: Registers Associated with Synchronous Slave Reception29517.0 Analog-to-Digital Converter (ADC) Module297FIGURE 17-1: ADC Block Diagram29717.1 ADC Configuration29817.1.1 Port Configuration29817.1.2 Channel Selection29817.1.3 ADC Voltage Reference29817.1.4 Selecting and Configuring Acquisition Time29817.1.5 Conversion Clock29917.1.6 Interrupts299TABLE 17-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies29917.1.7 Result Formatting300FIGURE 17-2: 10-Bit A/D Conversion Result Format30017.2 ADC Operation30117.2.1 Starting a Conversion301FIGURE 17-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, TACQ = 0)301FIGURE 17-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, TACQ = 4 TAD)30117.2.2 Completion of a Conversion30217.2.3 Discharge30217.2.4 Terminating a conversion30217.2.5 Delay Between Conversions30217.2.6 ADC Operation in Power- Managed Modes30217.2.7 ADC Operation During Sleep30217.2.8 Special Event Trigger30217.2.9 Peripheral Module Disable30217.2.10 A/D Conversion Procedure303EXAMPLE 17-1: A/D Conversion30317.3 Register Definitions: ADC Control304Register 17-1: ADCON0: A/D Control Register 0304Register 17-2: ADCON1: A/D Control Register 1305Register 17-3: ADCON2: A/D Control Register 2306Register 17-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 0307Register 17-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0307Register 17-6: ADRESH: ADC Result Register High (ADRESH) ADFM = 1307Register 17-7: ADRESL: ADC Result Register Low (ADRESL) ADFM = 130717.4 A/D Acquisition Requirements308EQUATION 17-1: Acquisition Time Example308FIGURE 17-5: Analog Input Model309FIGURE 17-6: ADC Transfer Function309TABLE 17-2: Registers Associated with A/D Operation310TABLE 17-3: Configuration Registers Associated with the ADC Module31018.0 Comparator Module31118.1 Comparator Overview311FIGURE 18-1: Single Comparator311FIGURE 18-2: Comparator C1/C2 Simplified Block Diagram31218.2 Comparator Control31318.2.1 Comparator Enable31318.2.2 Comparator Input Selection31318.2.3 Comparator Reference Selection31318.2.4 Comparator Output Selection31318.2.5 Comparator Output Polarity313TABLE 18-1: Comparator Output State vs. Input Conditions31318.2.6 Comparator Speed Selection31318.3 Comparator Response Time31318.4 Comparator Interrupt Operation31418.4.1 Presetting the Mismatch Latches314FIGURE 18-3: Comparator Interrupt Timing W/O CMxCON0 Read314FIGURE 18-4: Comparator Interrupt Timing With CMxCON0 Read31418.5 Operation During Sleep31518.6 Effects of a Reset31518.7 Analog Input Connection Considerations315FIGURE 18-5: Analog Input Model31518.8 Additional Comparator Features31618.8.1 Simultaneous Comparator Output Read31618.8.2 Internal Reference Selection31618.8.3 Comparator Hysteresis31618.8.4 Synchronizing Comparator Output to Timer131618.9 Register Definitions: Comparator Control317Register 18-1: CMxCON0: Comparator x Control Register317Register 18-2: CM2CON1: Comparator 1 and 2 Control Register318TABLE 18-2: Registers Associated with Comparator Module31919.0 Charge Time Measurement Unit (CTMU)321FIGURE 19-1: CTMU Block Diagram32119.1 CTMU Operation32219.1.1 Theory of Operation32219.1.2 Current Source32219.1.3 Edge Selection and Control32219.1.4 Edge Status32219.1.5 Interrupts32319.2 CTMU Module Initialization32319.3 Calibrating the CTMU Module32419.3.1 Current Source Calibration324FIGURE 19-2: CTMU Current Source Calibration Circuit324EXAMPLE 19-1: Setup for CTMU Calibration Routines325EXAMPLE 19-2: Current Calibration Routine32619.3.2 Capacitance Calibration327EXAMPLE 19-3: Capacitance Calibration Routine32819.4 Measuring Capacitance with the CTMU32919.4.1 Absolute Capacitance Measurement32919.4.2 Relative Charge Measurement329EXAMPLE 19-4: Routine for Capacitive Touch Switch33019.5 Measuring Time with the CTMU Module331FIGURE 19-3: Typical Connections and Internal Configuration for Time Measurement33119.6 Creating a Delay with the CTMU Module332FIGURE 19-4: Typical Connections and Internal Configuration for Pulse Delay Generation33219.7 Operation During Sleep/Idle Modes33219.7.1 Sleep Mode and Deep Sleep Modes33219.7.2 Idle Mode33219.8 CTMU Peripheral Module Disable (PMD)33219.9 Effects of a Reset on CTMU33319.10 Registers33319.11 Register Definitions: CTMU Control333Register 19-1: CTMUCONH: CTMU Control Register 0333Register 19-2: CTMUCONL: CTMU Control Register 1334Register 19-3: CTMUICON: CTMU current Control Register335TABLE 19-1: Registers Associated with CTMU Module33520.0 SR Latch33720.1 Latch Operation33720.2 Latch Output33720.3 DIVSRCLK Clock Generation33720.4 Effects of a Reset337FIGURE 20-1: DIVSRCLK Block Diagram338FIGURE 20-2: SR Latch Simplified Block Diagram338TABLE 20-1: DIVSRCLK Frequency table33920.5 Register Definitions: SR Latch Control340Register 20-1: SRCON0: SR Latch Control Register340Register 20-2: SRCON1: SR Latch Control Register 1341TABLE 20-2: Registers Associated with the SR Latch34121.0 Fixed Voltage Reference (FVR)34321.1 Independent Gain Amplifiers34321.2 FVR Stabilization Period343FIGURE 21-1: Voltage Reference Block Diagram34321.3 Register Definitions: FVR Control344Register 21-1: VREFCON0: Fixed Voltage Reference Control Register344TABLE 21-1: Summary of Registers Associated with Fixed Voltage Reference34422.0 Digital-to-Analog Converter (DAC) Module34522.1 Output Voltage Selection345EQUATION 22-1: DAC Output Voltage34522.2 Ratiometric Output Level34522.3 Low-Power Voltage State34522.4 Output Clamped to Positive Voltage Source34522.5 Output Clamped to Negative Voltage Source34522.6 DAC Voltage Reference Output345FIGURE 22-1: Digital-to-Analog Converter Block Diagram346FIGURE 22-2: Voltage Reference Output Buffer Example34622.7 Operation During Sleep34722.8 Effects of a Reset34722.9 Register Definitions: DAC Control347Register 22-1: VREFCON1: Voltage Reference Control Register 0347Register 22-2: VREFCON2: Voltage Reference Control Register 1348TABLE 22-1: Registers Associated with DAC Module34823.0 High/Low-Voltage Detect (HLVD)34923.1 Register - HLVD Control349Register 23-1: HLVDCON: High/Low-Voltage Detect Control Register34923.2 Operation350FIGURE 23-1: HLVD Module Block Diagram (with External Input)35023.3 HLVD Setup35123.4 Current Consumption35123.5 HLVD Start-up Time351FIGURE 23-2: Low-Voltage Detect Operation (VDIRMAG = 0)351FIGURE 23-3: High-Voltage Detect Operation (VDIRMAG = 1)35223.6 Applications352FIGURE 23-4: Typical Low-Voltage Detect Application35223.7 Operation During Sleep35323.8 Effects of a Reset353TABLE 23-1: Registers Associated with High/Low-Voltage Detect Module35324.0 Special Features of the CPU35524.1 Configuration Bits355TABLE 24-1: Configuration Bits and Device IDs35624.2 Register Definitions: Configuration Word357Register 24-1: CONFIG1H: Configuration Register 1 High357Register 24-2: CONFIG2L: Configuration Register 2 Low358Register 24-3: CONFIG2H: Configuration Register 2 High359Register 24-4: CONFIG3H: Configuration Register 3 High360Register 24-5: CONFIG4L: Configuration Register 4 Low361Register 24-6: CONFIG5L: Configuration Register 5 Low361Register 24-7: CONFIG5H: Configuration Register 5 High362Register 24-8: CONFIG6L: Configuration Register 6 Low362Register 24-9: CONFIG6H: Configuration Register 6 High363Register 24-10: CONFIG7L: Configuration Register 7 Low363Register 24-11: CONFIG7H: Configuration Register 7 High364Register 24-12: DEVID1: Device ID Register 1364Register 24-13: DEVID2: Device ID Register 2364TABLE 24-2: Device ID Table for the PIC18(L)F2X/4XK22 Family36524.3 Watchdog Timer (WDT)366FIGURE 24-1: WDT Block Diagram36624.3.1 Control Register36724.4 Register Definitions: WDT Control367Register 24-14: WDTCON: Watchdog Timer Control Register367TABLE 24-3: Registers Associated with Watchdog Timer367TABLE 24-4: Configuration Registers Associated with Watchdog Timer36724.5 Program Verification and Code Protection368FIGURE 24-2: Code-Protected Program Memory for PIC18(L)F2X/4XK22368TABLE 24-5: Configuration Registers Associated with Code Protection36824.5.1 Program Memory Code Protection369FIGURE 24-3: Table Write (WRTn) Disallowed369FIGURE 24-4: External Block Table Read (EBTRn) Disallowed370FIGURE 24-5: External Block Table Read (EBTRn) Allowed37024.5.2 Data EEPROM Code Protection37124.5.3 Configuration Register Protection37124.6 ID Locations37124.7 In-Circuit Serial Programming37124.8 In-Circuit Debugger371TABLE 24-6: Debugger Resources37124.9 Single-Supply ICSP Programming37125.0 Instruction Set Summary37325.1 Standard Instruction Set373TABLE 25-1: Opcode Field Descriptions374FIGURE 25-1: General Format for Instructions375TABLE 25-2: PIC18(L)F2X/4XK22 Instruction Set37625.1.1 Standard Instruction Set37925.2 Extended Instruction Set41525.2.1 Extended Instruction Syntax415TABLE 25-3: Extensions to the PIC18 Instruction Set41525.2.2 Extended Instruction Set41625.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode42025.2.4 Considerations when Enabling the Extended Instruction Set42025.2.5 Special Considerations with Microchip MPLAB® IDE Tools42226.0 Development Support42326.1 MPLAB Integrated Development Environment Software42326.2 MPLAB C Compilers for Various Device Families42426.3 HI-TECH C for Various Device Families42426.4 MPASM Assembler42426.5 MPLINK Object Linker/ MPLIB Object Librarian42426.6 MPLAB Assembler, Linker and Librarian for Various Device Families42426.7 MPLAB SIM Software Simulator42526.8 MPLAB REAL ICE In-Circuit Emulator System42526.9 MPLAB ICD 3 In-Circuit Debugger System42526.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express42526.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express42626.12 MPLAB PM3 Device Programmer42626.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits42627.0 Electrical Characteristics427Absolute Maximum Ratings (†)427FIGURE 27-1: PIC18LF2X/4XK22 Family Voltage-Frequency Graph (Industrial Temperature)428FIGURE 27-2: PIC18LF2X/4XK22 Family Voltage-Frequency Graph (Extended Temperature)428FIGURE 27-3: PIC18F2X/4XK22 Family Voltage-Frequency Graph (Industrial Temperature)429FIGURE 27-4: PIC18F2X/4XK22 Family Voltage-Frequency Graph (Extended Temperature)42927.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK2243027.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK2243127.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK2243327.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK2243527.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK2243727.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/4XK2243827.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK2243927.8 DC Characteristics: Input/Output Characteristics, PIC18(L)F2X/4XK2244127.9 Memory Programming Requirements44327.10 Analog Characteristics444TABLE 27-1: Comparator Specifications444TABLE 27-2: DIGITAL-TO-ANALOG CONVERTER (DAC) Specifications444TABLE 27-3: Fixed Voltage Reference (FVR) Specifications445TABLE 27-4: CHARGE TIME MEASUREMENT UNIT (CTMU) Specifications445FIGURE 27-5:446TABLE 27-5: High/Low-Voltage Detect Characteristics44627.11 AC (Timing) Characteristics44727.11.1 Timing Parameter Symbology44727.11.2 Timing Conditions448TABLE 27-6: Temperature and Voltage Specifications – AC448FIGURE 27-6: Load Conditions for Device Timing Specifications44827.11.3 Timing Diagrams and Specifications449FIGURE 27-7: External Clock Timing (All Modes Except PLL)449TABLE 27-7: External Clock Timing Requirements449TABLE 27-8: PLL Clock Timing Specifications450TABLE 27-9: AC Characteristics: Internal Oscillators Accuracy PIC18(L)F46K22450FIGURE 27-8: CLKOUT and I/O Timing451TABLE 27-10: CLKOUT and I/O Timing Requirements451FIGURE 27-9: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing452FIGURE 27-10: Brown-out Reset Timing452TABLE 27-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements453FIGURE 27-11: Timer0 and Timer1 External Clock Timings453TABLE 27-12: Timer0 and Timer1/3/5 External Clock Requirements454FIGURE 27-12: Capture/Compare/PWM Timings (All CCP Modules)454TABLE 27-13: Capture/Compare/PWM Requirements (All CCP Modules)455FIGURE 27-13: Example SPI Master Mode Timing (CKE = 0)455TABLE 27-14: Example SPI Mode Requirements (Master Mode, CKE = 0 or 1)456FIGURE 27-14: Example SPI Master Mode Timing (CKE = 1)456FIGURE 27-15: Example SPI Slave Mode Timing (CKE = 0)457TABLE 27-15: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0 or 1)457FIGURE 27-16: Example SPI Slave Mode Timing (CKE = 1)458FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing458TABLE 27-16: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)459FIGURE 27-18: I2C™ Bus Data Timing459TABLE 27-17: I2C™ Bus Data Requirements (Slave Mode)460FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms461TABLE 27-18: Master SSP I2C™ Bus Start/Stop Bits Requirements461FIGURE 27-20: Master SSP I2C™ Bus Data Timing461TABLE 27-19: Master SSP I2C™ Bus Data Requirements462FIGURE 27-21: EUSART Synchronous Transmission (Master/Slave) Timing463TABLE 27-20: EUSART Synchronous Transmission Requirements463FIGURE 27-22: EUSART Synchronous Receive (Master/Slave) Timing463TABLE 27-21: EUSART Synchronous Receive Requirements463TABLE 27-22: A/D Converter Characteristics: PIC18(L)F2X/4XK22464FIGURE 27-23: A/D Conversion Timing464TABLE 27-23: A/D Conversion Requirements PIC18(L)F2X/4XK2246528.0 DC and AC Characteristics Graphs and Charts46729.0 Packaging Information52329.1 Package Marking Information52329.2 Package Details526Appendix A: Revision History545Revision A (February 2010)545Revision B (April 2010)545Revision C (July 2010)545Revision D (November 2010)545Revision E (January 2012)545Revision F (May 2012)545Appendix B: Device Differences546TABLE B-1: Device Differences546INDEX547A547B547C547D549E549F550G550H550I550L551M551N551O551P551R552S553T553V555W555X555The Microchip Web Site557Customer Change Notification Service557Customer Support557Reader Response558Product Identification System559Worldwide Sales560サイズ: 9.21MBページ数: 560Language: Englishマニュアルを開く