Microchip Technology MA180023 マニュアル

目次

• Power Management Features with nanoWatt XLP for Extreme Low Power:

  3
• Special Microcontroller Features:

  3
• Peripheral Highlights:

  3
• Peripheral Highlights (Continued):

  3
• Flexible Oscillator Structure:

  3
• Pin Diagrams

  5
• Pin Diagrams (Continued)

  6
• Pin Diagrams (Continued)

  7
• Table of Contents

  8
• Most Current Data Sheet

  9
• Errata

  9
• Customer Notification System

  9
• 1.0 Device Overview

  11
  • 1.1 Core Features

    11
    • 1.1.1 nanoWatt Technology

      11
    • 1.1.2 Oscillator Options and Features

      11
    • 1.1.3 Expanded Memory

      11
    • 1.1.4 Extended Instruction Set

      12
    • 1.1.5 Easy Migration

      12
  • 1.2 Other Special Features

    12
  • 1.3 Details on Individual Family Devices

    12
    • TABLE 1-1: Device Features for the PIC18F2XJ11 (28-pin Devices)

      13
    • TABLE 1-2: Device Features for the PIC18F4XJ11 (44-pin Devices)

      13
    • FIGURE 1-1: PIC18F2XJ11 (28-pin) Block Diagram

      14
    • FIGURE 1-2: PIC18F4XJ11 (44-pin) Block Diagram

      15
    • TABLE 1-3: PIC18F2XJ11 Pinout I/O Descriptions

      16
    • TABLE 1-4: PIC18F4XJ11 Pinout I/O Descriptions

      22
• 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers

  31
  • 2.1 Basic Connection Requirements

    31
    • FIGURE 2-1: Recommended Minimum connections

      31
  • 2.2 Power Supply Pins

    32
    • 2.2.1 Decoupling Capacitors

      32
    • 2.2.2 Tank Capacitors

      32
  • 2.3 Master Clear (MCLR) Pin

    32
    • FIGURE 2-2: Example of MCLR Pin Connections

      32
  • 2.4 Voltage Regulator Pins (Vcap/ Vddcore)

    33
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      33
    • TABLE 2-1: Suitable Capacitor Equivalents

      33
    • 2.4.1 Considerations for Ceramic Capacitors

      34
      • FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics

        34
  • 2.5 ICSP Pins

    34
  • 2.6 External Oscillator Pins

    35
  • 2.7 Unused I/Os

    35
    • FIGURE 2-5: Suggested Placement of the Oscillator Circuit

      35
• 3.0 Oscillator Configurations

  37
  • 3.1 Overview

    37
    • 3.1.1 Oscillator Control

      37
  • 3.2 Oscillator Types

    37
    • TABLE 3-1: Oscillator Modes

      37
    • 3.2.1 Oscillator Modes

      38
      • FIGURE 3-1: PIC18F46J11 family Clock Diagram

        38
    • 3.2.2 Crystal Oscillator/Ceramic Resonators

      39
      • FIGURE 3-2: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)

        39
      • TABLE 3-2: Capacitor Selection for Ceramic Resonators

        39
      • TABLE 3-3: Capacitor Selection for Crystal Oscillator

        39
    • 3.2.3 External Clock Input

      40
      • FIGURE 3-3: External Clock Input Operation (EC and ECPLL Configuration)

        40
    • 3.2.4 PLL Frequency Multiplier

      40
    • 3.2.5 Internal Oscillator Block

      40
      • Register 3-1: OSCTUNE: Oscillator Tuning Register (Access F9Bh)

        42
  • 3.3 Clock Sources and Oscillator Switching

    42
    • 3.3.1 Oscillator Control Register

      43
    • 3.3.2 Oscillator Transitions

      43
      • Register 3-2: OSCCON: Oscillator Control Register (Access FD3h)

        44
  • 3.4 Reference Clock Output

    45
    • Register 3-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (Banked F3Dh)

      45
  • 3.5 Effects of Power-Managed Modes on Various Clock Sources

    46
  • 3.6 Power-up Delays

    46
• 4.0 Low-Power Modes

  47
  • 4.1 Selecting Power-Managed Modes

    47
    • 4.1.1 Clock Sources

      47
    • 4.1.2 Entering Power-Managed Modes

      47
      • TABLE 4-1: Low-Power Modes

        48
    • 4.1.3 Clock Transitions and Status Indicators

      48
    • 4.1.4 Multiple Sleep Commands

      48
  • 4.2 Run Modes

    48
    • 4.2.1 PRI_RUN Mode

      48
    • 4.2.2 SEC_RUN Mode

      48
      • FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode

        49
      • FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        49
    • 4.2.3 RC_RUN Mode

      50
      • FIGURE 4-3: Transition Timing to RC_RUN Mode

        50
      • FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        50
  • 4.3 Sleep Mode

    51
    • FIGURE 4-5: Transition Timing for Entry to Sleep Mode

      51
    • FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)

      51
  • 4.4 Idle Modes

    52
    • 4.4.1 PRI_IDLE Mode

      52
    • 4.4.2 SEC_IDLE Mode

      52
      • FIGURE 4-7: Transition Timing for Entry to Idle Mode

        53
      • FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode

        53
    • 4.4.3 RC_IDLE Mode

      54
  • 4.5 Exiting Idle and Sleep Modes

    54
    • 4.5.1 Exit By Interrupt

      54
    • 4.5.2 Exit By WDT Time-out

      54
    • 4.5.3 Exit By Reset

      54
    • 4.5.4 Exit Without an Oscillator Start-up Delay

      54
  • 4.6 Deep Sleep Mode

    54
    • 4.6.1 Preparing For Deep Sleep

      55
    • 4.6.2 I/O PINS DURING DEEP SLEEP

      55
    • 4.6.3 Deep Sleep Wake-up Sources

      56
    • 4.6.4 Deep Sleep Watchdog Timer (DSWDT)

      56
    • 4.6.5 Deep Sleep Brown Out Reset (DSBOR)

      56
    • 4.6.6 RTCC Peripheral and Deep Sleep

      56
    • 4.6.7 Typical Deep Sleep Sequence

      57
    • 4.6.8 Deep Sleep Fault Detection

      57
    • 4.6.9 Deep Sleep Mode Registers

      58
      • Register 4-1: DSCONH: Deep Sleep Control High Byte Register (Banked F4Dh)

        58
      • Register 4-2: DSCONL: Deep Sleep Control Low Byte Register (Banked F4Ch)

        58
      • Register 4-3: DSGPR0: Deep Sleep Persistent General Purpose Register 0 (Banked F4Eh)

        59
      • Register 4-4: DSGPR1: Deep Sleep Persistent General Purpose Register 1 (Banked F4Fh)

        59
      • Register 4-5: DSWAKEH: Deep Sleep Wake High Byte Register (Banked F4Bh)

        60
      • Register 4-6: DSWAKEL: Deep Sleep Wake Low Byte Register (Banked F4Ah)

        60
  • 4.7 Ultra Low-Power Wake-up

    61
    • FIGURE 4-9: Serial Resistor

      61
    • EXAMPLE 4-1: Ultra Low-Power Wake-up Initialization

      62
• 5.0 Reset

  63
  • 5.1 RCON Register

    63
    • FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit

      63
    • Register 5-1: RCON: Reset Control Register (Access FD0h)

      64
  • 5.2 Master Clear (MCLR)

    65
  • 5.3 Power-on Reset (POR)

    65
  • 5.4 Brown-out Reset (BOR)

    65
    • 5.4.1 Detecting BOR

      65
  • 5.5 Configuration Mismatch (CM)

    66
  • 5.6 Power-up Timer (PWRT)

    66
    • 5.6.1 Time-out Sequence

      66
      • FIGURE 5-2: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        66
      • FIGURE 5-3: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1

        67
      • FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2

        67
      • FIGURE 5-5: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        67
  • 5.7 Reset State of Registers

    68
    • TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register

      68
    • TABLE 5-2: Initialization Conditions for All Registers

      69
• 6.0 Memory Organization

  77
  • 6.1 Program Memory Organization

    77
    • FIGURE 6-1: Memory Maps for PIC18F46J11 family Devices

      77
    • 6.1.1 Hard Memory Vectors

      78
      • FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F46J11 family Devices

        78
    • 6.1.2 Flash Configuration Words

      78
      • TABLE 6-1: Flash Configuration Word for PIC18F46J11 family Devices

        78
    • 6.1.3 Program Counter

      79
    • 6.1.4 Return Address Stack

      79
      • FIGURE 6-3: Return Address Stack and Associated Registers

        79
      • Register 6-1: STKPTR: Stack Pointer Register (Access FFCh)

        80
    • 6.1.5 Fast Register Stack (FRS)

      81
      • EXAMPLE 6-1: Fast Register Stack Code Example

        81
    • 6.1.6 Look-up Tables in Program Memory

      81
      • EXAMPLE 6-2: Computed GOTO Using an Offset Value

        81
  • 6.2 PIC18 Instruction Cycle

    82
    • 6.2.1 Clocking Scheme

      82
    • 6.2.2 Instruction Flow/Pipelining

      82
      • FIGURE 6-4: Clock/ Instruction Cycle

        82
      • EXAMPLE 6-3: Instruction Pipeline Flow

        82
    • 6.2.3 Instructions in Program Memory

      83
      • FIGURE 6-5: Instructions in Program Memory

        83
    • 6.2.4 Two-Word Instructions

      83
      • EXAMPLE 6-4: Two-Word Instructions

        83
  • 6.3 Data Memory Organization

    84
    • 6.3.1 Bank Select Register

      84
      • FIGURE 6-6: Data Memory Map for PIC18F46J11 family Devices

        85
      • FIGURE 6-7: Use of the Bank Select Register (Direct Addressing)

        86
    • 6.3.2 Access Bank

      86
    • 6.3.3 General Purpose Register File

      86
    • 6.3.4 Special Function Registers

      87
      • TABLE 6-2: Access Bank Special Function Register Map

        87
      • TABLE 6-3: Non-Access Bank Special Function Register Map

        88
      • TABLE 6-4: Register File Summary (PIC18F46J11 Family)

        90
    • 6.3.5 STATUS Register

      96
      • Register 6-2: Status Register (Access FD8h)

        96
  • 6.4 Data Addressing Modes

    97
    • 6.4.1 Inherent and Literal Addressing

      97
    • 6.4.2 Direct Addressing

      97
    • 6.4.3 Indirect Addressing

      97
      • EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing

        97
      • FIGURE 6-8: Indirect Addressing

        98
  • 6.5 Program Memory and the Extended Instruction Set

    99
  • 6.6 Data Memory and the Extended Instruction Set

    99
    • 6.6.1 Indexed Addressing with Literal Offset

      100
    • 6.6.2 Instructions Affected By Indexed Literal Offset Mode

      100
      • FIGURE 6-9: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        101
    • 6.6.3 Mapping the Access Bank in Indexed Literal Offset Mode

      102
    • 6.6.4 BSR in Indexed Literal Offset Mode

      102
      • FIGURE 6-10: Remapping the Access Bank with Indexed Literal Offset Addressing

        102
• 7.0 Flash Program Memory

  103
  • 7.1 Table Reads and Table Writes

    103
    • FIGURE 7-1: TABLE READ Operation

      103
    • FIGURE 7-2: TABLE WRITE Operation

      104
  • 7.2 Control Registers

    104
    • 7.2.1 EECON1 and EECON2 Registers

      104
      • Register 7-1: EECON1: EEPROM Control Register 1 (Access FA6h)

        105
    • 7.2.2 Table Latch Register (TABLAT)

      106
    • 7.2.3 Table Pointer Register (TBLPTR)

      106
    • 7.2.4 Table Pointer Boundaries

      106
      • TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        106
      • FIGURE 7-3: Table Pointer Boundaries Based on Operation

        106
  • 7.3 Reading the Flash Program Memory

    107
    • FIGURE 7-4: Reads from Flash Program Memory

      107
    • EXAMPLE 7-1: Reading a Flash Program Memory Word

      107
  • 7.4 Erasing Flash Program Memory

    108
    • 7.4.1 Flash Program Memory Erase Sequence

      108
      • EXAMPLE 7-2: Erasing Flash Program Memory

        108
  • 7.5 Writing to Flash Program Memory

    109
    • FIGURE 7-5: Table Writes to Flash Program Memory

      109
    • 7.5.1 Flash Program Memory Write Sequence

      109
      • EXAMPLE 7-3: Writing to Flash Program Memory

        110
    • 7.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING).

      111
      • EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY

        111
    • 7.5.3 Write Verify

      112
    • 7.5.4 Unexpected Termination of Write Operation

      112
  • 7.6 Flash Program Operation During Code Protection

    112
    • TABLE 7-2: Registers Associated with Program Flash Memory

      112
• 8.0 8 X 8 Hardware Multiplier

  113
  • 8.1 Introduction

    113
  • 8.2 Operation

    113
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine

      113
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine

      113
    • TABLE 8-1: Performance Comparison for Various Multiply Operations

      113
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm

      114
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine

      114
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm

      114
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine

      114
• 9.0 Interrupts

  115
  • FIGURE 9-1: PIC18F46J11 family Interrupt Logic

    116
  • 9.1 INTCON Registers

    117
    • Register 9-1: INTCON: Interrupt Control Register (Access FF2h)

      117
    • Register 9-2: INTCON2: Interrupt Control Register 2 (Access FF1h)

      118
    • Register 9-3: INTCON3: Interrupt Control Register 3 (Access FF0h)

      119
  • 9.2 PIR Registers

    120
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1 (Access F9Eh)

      120
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2 (Access FA1h)

      121
    • Register 9-6: PIR3: Peripheral Interrupt Request (Flag) Register 3 (Access FA4h)

      122
  • 9.3 PIE Registers

    123
    • Register 9-7: PIE1: Peripheral Interrupt Enable Register 1 (Access F9Dh)

      123
    • Register 9-8: PIE2: Peripheral Interrupt Enable Register 2 (Access FA0h)

      124
    • Register 9-9: PIE3: Peripheral Interrupt Enable Register 3 (Access FA3h)

      125
  • 9.4 IPR Registers

    126
    • Register 9-10: IPR1: Peripheral Interrupt Priority Register 1 (Access F9Fh)

      126
    • Register 9-11: IPR2: Peripheral Interrupt Priority Register 2 (Access FA2h)

      127
    • Register 9-12: IPR3: Peripheral Interrupt Priority Register 3 (Access FA5h)

      128
  • 9.5 RCON Register

    129
    • Register 9-13: RCON: Reset Control Register (Access FD0h)

      129
  • 9.6 INTx Pin Interrupts

    130
  • 9.7 TMR0 Interrupt

    130
  • 9.8 PORTB Interrupt-on-Change

    130
  • 9.9 Context Saving During Interrupts

    130
    • EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM

      130
• 10.0 I/O Ports

  131
  • FIGURE 10-1: Generic I/O Port Operation

    131
  • 10.1 I/O Port Pin Capabilities

    131
    • 10.1.1 Pin Output Drive

      131
      • TABLE 10-1: Output Drive Levels

        131
    • 10.1.2 Input Pins and Voltage Considerations

      131
      • TABLE 10-2: Input Voltage Levels

        131
    • 10.1.3 Interfacing to a 5V System

      132
      • FIGURE 10-2: +5V System Hardware Interface

        132
      • EXAMPLE 10-1: Communicating with the +5V System

        132
    • 10.1.4 Open-Drain Outputs

      132
      • FIGURE 10-3: Using the Open-Drain Output (USART Shown as Example)

        132
    • 10.1.5 TTL Input Buffer Option

      132
      • Register 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL Register 1 (Banked F42h)

        133
      • Register 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL Register 2 (Banked F41h)

        133
      • Register 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL Register 3 (Banked F40h)

        134
      • Register 10-4: PADCFG1: Pad Configuration Control Register 1 (Banked F3Ch)

        134
  • 10.2 PORTA, TRISA and LATA Registers

    135
    • EXAMPLE 10-2: Initializing PORTA

      135
    • TABLE 10-3: PORTA I/O Summary

      136
    • TABLE 10-4: Summary of Registers Associated with PORTA

      137
  • 10.3 PORTB, TRISB and LATB Registers

    138
    • EXAMPLE 10-3: Initializing PORTB

      138
    • TABLE 10-5: PORTB I/O Summary

      139
    • TABLE 10-6: Summary of Registers Associated with PORTB

      141
  • 10.4 PORTC, TRISC and LATC Registers

    142
    • EXAMPLE 10-4: Initializing PORTC

      142
    • TABLE 10-7: PORTC I/O Summary

      143
    • TABLE 10-8: Summary of Registers Associated with PORTC

      144
  • 10.5 PORTD, TRISD and LATD Registers

    145
    • EXAMPLE 10-5: Initializing PORTD

      145
    • TABLE 10-9: PORTD I/O Summary

      146
    • TABLE 10-10: Summary of Registers Associated with PORTD

      147
  • 10.6 PORTE, TRISE and LATE Registers

    148
    • EXAMPLE 10-6: Initializing PORTE

      148
    • TABLE 10-11: PORTE I/O Summary

      149
    • TABLE 10-12: Summary of Registers Associated with PORTE

      149
  • 10.7 Peripheral Pin Select (PPS)

    150
    • 10.7.1 Available Pins

      150
    • 10.7.2 Available Peripherals

      150
    • 10.7.3 Controlling Peripheral Pin Select

      150
      • TABLE 10-13: Selectable INPUT SOURCES (MAPS Input TO FUNCTION)(1)

        151
      • TABLE 10-14: Selectable OUTPUT SOURCES (MAPS Function TO Output)

        152
    • 10.7.4 Controlling Configuration Changes

      153
    • 10.7.5 Considerations for Peripheral Pin Selection

      153
      • EXAMPLE 10-7: Configuring EUSART2 Input and OUtput Functions

        154
    • 10.7.6 Peripheral Pin Select Registers

      155
      • Register 10-5: PPSCON: Peripheral Pin Select Input Register 0 (Banked EFFh)(1)

        155
      • Register 10-6: RPINR1: Peripheral Pin Select Input Register 1 (Banked EE7h)

        156
      • Register 10-7: RPINR2: Peripheral Pin Select Input Register 2 (Banked EE8h)

        156
      • Register 10-8: RPINR3: Peripheral Pin Select Input Register 3 (Banked EE9h)

        156
      • Register 10-9: RPINR4: Peripheral Pin Select Input Register 4 (Banked EEAh)

        157
      • Register 10-10: RPINR6: Peripheral Pin Select Input Register 6 (Banked EECh)

        157
      • Register 10-11: RPINR7: Peripheral Pin Select Input Register 7 (Banked EEDh)

        157
      • Register 10-12: RPINR8: Peripheral Pin Select Input Register 8 (Banked EEEh)

        158
      • Register 10-13: RPINR12: Peripheral Pin Select Input Register 12 (Banked EF2h)

        158
      • Register 10-14: RPINR13: Peripheral Pin Select Input Register 13 (Banked EF3h)

        158
      • Register 10-15: RPINR16: Peripheral Pin Select Input Register 16 (Banked EF6h)

        159
      • Register 10-16: RPINR17: Peripheral Pin Select Input Register 17 (Banked EF7h)

        159
      • Register 10-17: RPINR21: Peripheral Pin Select Input Register 21 (Banked EFBh)

        159
      • Register 10-18: RPINR22: Peripheral Pin Select Input Register 22 (Banked EFCh)

        160
      • Register 10-19: RPINR23: Peripheral Pin Select Input Register 23 (Banked EFDh)

        160
      • Register 10-20: RPINR24: Peripheral Pin Select Input Register 24 (Banked EFEh)

        160
      • Register 10-21: RPOR0: Peripheral Pin Select Output Register 0 (Banked EC6h)(1)

        161
      • Register 10-22: RPOR1: Peripheral Pin Select Output Register 1 (Banked EC7h)

        161
      • Register 10-23: RPOR2: Peripheral Pin Select Output Register 2 (Banked EC8h)

        161
      • Register 10-24: RPOR3: Peripheral Pin Select Output Register 3 (Banked EC9h)

        162
      • Register 10-25: RPOR4: Peripheral Pin Select Output Register 4 (Banked ECAh)

        162
      • Register 10-26: RPOR5: Peripheral Pin Select Output Register 5 (Banked ECBh)

        162
      • Register 10-27: RPOR6: Peripheral Pin Select Output Register 6 (Banked ECCh)

        163
      • Register 10-28: RPOR7: Peripheral Pin Select Output Register 7 (Banked ECDh)

        163
      • Register 10-29: RPOR8: Peripheral Pin Select Output Register 8 (Banked ECEh)

        163
      • Register 10-30: RPOR9: Peripheral Pin Select Output Register 9 (Banked ECFh)

        164
      • Register 10-31: RPOR10: Peripheral Pin Select Output Register 10 (Banked ED0h)

        164
      • Register 10-32: RPOR11: Peripheral Pin Select Output Register 11 (Banked ED1h)

        164
      • Register 10-33: RPOR12: Peripheral Pin Select Output Register 12 (Banked ED2h)

        165
      • Register 10-34: RPOR13: Peripheral Pin Select Output Register 13 (Banked ED3h)

        165
      • Register 10-35: RPOR14: Peripheral Pin Select Output Register 14 (Banked ED4h)

        165
      • Register 10-36: RPOR15: Peripheral Pin Select Output Register 15 (Banked ED5h)

        166
      • Register 10-37: RPOR16: Peripheral Pin Select Output Register 16 (Banked ED6h)

        166
      • Register 10-38: RPOR17: Peripheral Pin Select Output Register 17 (Banked ED7h)

        166
      • Register 10-39: RPOR18: Peripheral Pin Select Output Register 18 (Banked ED8h)

        167
      • Register 10-40: RPOR19: Peripheral Pin Select Output Register 19 (Banked ED9h)(1)

        167
      • Register 10-41: RPOR20: Peripheral Pin Select Output Register 20 (Banked EDAh)(1)

        167
      • Register 10-42: RPOR21: Peripheral Pin Select Output Register 21 (Banked EDBh)(1)

        168
      • Register 10-43: RPOR22: Peripheral Pin Select Output Register 22 (Banked EDCh)(1)

        168
      • Register 10-44: RPOR23: Peripheral Pin Select Output Register 23 (Banked EDDh)(1)

        168
      • Register 10-45: RPOR24: Peripheral Pin Select Output Register 24 (Banked EDEh)(1)

        169
• 11.0 Parallel Master Port (PMP)

  171
  • FIGURE 11-1: PMP Module Overview

    171
  • 11.1 Module Registers

    172
    • 11.1.1 CONTROL REGISTERS

      172
      • Register 11-1: PMCONH: Parallel Port Control Register High Byte (Banked F5Fh)(1)

        172
      • Register 11-2: PMCONL: Parallel Port Control Register Low Byte (Banked F5Eh)(1)

        173
      • Register 11-3: PMMODEH: Parallel Port Mode Register High Byte (Banked F5Dh)(1)

        174
      • Register 11-4: PMMODEL: Parallel Port Mode Register Low Byte (Banked F5Ch)(1)

        175
      • Register 11-5: PMEH: Parallel Port Enable Register High Byte (Banked F57h)(1)

        176
      • Register 11-6: PMEL: Parallel Port Enable Register Low Byte (Banked F56h)(1)

        176
      • Register 11-7: PMSTATH: Parallel Port Status Register High Byte (Banked F55h)(1)

        177
      • Register 11-8: PMSTATL: Parallel Port Status Register Low Byte (Banked F54h)(1)

        177
    • 11.1.2 Data Registers

      178
    • 11.1.3 Pad Configuration Control Register

      178
      • Register 11-9: PMADDRH: Parallel Port Address Register HIGH BYTE – MASTER MODES ONLY (Access F6Fh)(1)

        179
      • Register 11-10: PMADDRL: Parallel Port Address Register Low BYTE – MASTER MODES ONLY (Access F6Eh)(1)

        179
  • 11.2 Slave Port Modes

    180
    • 11.2.1 Legacy Mode (PSP)

      180
      • FIGURE 11-2: Legacy Parallel Slave Port Example

        180
    • 11.2.2 WRITE TO SLAVE PORT

      181
    • 11.2.3 READ FROM SLAVE PORT

      181
      • FIGURE 11-3: Parallel Slave Port Write Waveforms

        181
      • FIGURE 11-4: Parallel Slave Port Read Waveforms

        181
    • 11.2.4 Buffered Parallel Slave Port Mode

      182
      • FIGURE 11-5: Parallel Master/Slave Connection Buffered Example

        182
    • 11.2.5 Addressable Parallel Slave Port Mode

      183
      • TABLE 11-1: Slave Mode Buffer Addressing

        183
      • FIGURE 11-6: Parallel Master/Slave Connection Addressed Buffer Example

        183
      • FIGURE 11-7: Parallel Slave Port Read Waveforms

        183
      • FIGURE 11-8: Parallel Slave Port Write Waveforms

        184
  • 11.3 MASTER PORT MODES

    185
    • 11.3.1 PMP and I/O Pin Control

      185
    • 11.3.2 READ/WRITE CONTROL

      185
    • 11.3.3 DATA WIDTH

      185
    • 11.3.4 ADDRESS MULTIPLEXING

      185
      • FIGURE 11-9: Demultiplexed Addressing Mode (Separate Read and Write Strobes with Chip Select)

        186
      • FIGURE 11-10: Partially Multiplexed Addressing Mode (Separate Read and Write Strobes with Chip Select)

        186
      • FIGURE 11-11: Fully Multiplexed Addressing Mode (Separate Read and Write Strobes with Chip Select)

        186
    • 11.3.5 Chip Select Features

      187
    • 11.3.6 AUTO-INCREMENT/DECREMENT

      187
    • 11.3.7 WAIT STATES

      187
    • 11.3.8 Read Operation

      187
    • 11.3.9 Write Operation

      187
    • 11.3.10 Parallel Master Port Status

      187
    • 11.3.11 Master Mode Timing

      188
      • FIGURE 11-12: Read and Write Timing, 8-bit Data, Demultiplexed Address

        188
      • FIGURE 11-13: Read Timing, 8-bit Data, Partially Multiplexed Address

        188
      • FIGURE 11-14: Read Timing, 8-bit Data, Wait States Enabled, Partially Multiplexed Address

        188
      • FIGURE 11-15: Write Timing, 8-bit Data, Partially Multiplexed Address

        189
      • FIGURE 11-16: Write Timing, 8-bit Data, Wait States Enabled, Partially Multiplexed Address

        189
      • FIGURE 11-17: Read Timing, 8-bit Data, Partially Multiplexed Address, Enable Strobe

        189
      • FIGURE 11-18: Write Timing, 8-bit Data, Partially Multiplexed Address, Enable Strobe

        190
      • FIGURE 11-19: Read Timing, 8-bit Data, Fully Multiplexed 16-bit Address

        190
      • FIGURE 11-20: Write Timing, 8-bit Data, Fully Multiplexed 16-bit Address

        190
      • FIGURE 11-21: Read Timing, 16-bit Data, Demultiplexed Address

        191
      • FIGURE 11-22: Write Timing, 16-bit Data, Demultiplexed Address

        191
      • FIGURE 11-23: Read Timing, 16-bit Multiplexed Data, Partially Multiplexed Address

        191
      • FIGURE 11-24: Write Timing, 16-bit Multiplexed Data, Partially Multiplexed Address

        192
      • FIGURE 11-25: Read Timing, 16-bit Multiplexed Data, Fully Multiplexed 16-bit Address

        192
      • FIGURE 11-26: Write Timing, 16-bit Multiplexed Data, Fully Multiplexed 16-bit Address

        192
  • 11.4 Application Examples

    193
    • 11.4.1 Multiplexed Memory or Peripheral

      193
      • FIGURE 11-27: Example – Multiplexed Addressing Application

        193
    • 11.4.2 Partially Multiplexed Memory or Peripheral

      193
      • FIGURE 11-28: Example of a Partially Multiplexed Addressing Application

        193
      • FIGURE 11-29: Example of an 8-bit Multiplexed Address and Data Application

        193
    • 11.4.3 Parallel EEPROM Example

      194
      • FIGURE 11-30: Parallel EEPROM Example (Up to 15-bit Address, 8-bit Data)

        194
      • FIGURE 11-31: Parallel EEPROM Example (Up to 15-bit Address, 16-bit Data)

        194
    • 11.4.4 LCD Controller Example

      194
      • FIGURE 11-32: LCD Control Example (Byte Mode Operation)

        194
      • TABLE 11-2: Registers Associated with PMP Module

        195
• 12.0 Timer0 Module

  197
  • Register 12-1: T0CON: Timer0 Control Register (Access FD5h)

    197
  • 12.1 Timer0 Operation

    198
  • 12.2 Timer0 Reads and Writes in 16-Bit Mode

    198
    • FIGURE 12-1: Timer0 Block Diagram (8-bit Mode)

      198
    • FIGURE 12-2: Timer0 Block Diagram (16-bit Mode)

      198
  • 12.3 Prescaler

    199
    • 12.3.1 Switching Prescaler Assignment

      199
  • 12.4 Timer0 Interrupt

    199
    • TABLE 12-1: Registers Associated with Timer0

      199
• 13.0 Timer1 Module

  201
  • Register 13-1: T1CON: Timer1 Control Register (Access FCDh)

    201
  • 13.1 Timer1 Gate Control Register

    202
    • Register 13-2: T1GCON: Timer1 Gate Control Register (F9Ah)(1)

      202
    • Register 13-3: TCLKCON: Timer clock control register (Banked F52h)

      203
  • 13.2 Timer1 Operation

    204
  • 13.3 Clock Source Selection

    204
    • 13.3.1 INTERNAL CLOCK SOURCE

      204
    • 13.3.2 EXTERNAL CLOCK SOURCE

      204
      • TABLE 13-1: Timer1 Clock Source Selection

        204
      • FIGURE 13-1: Timer1 Block Diagram

        205
  • 13.4 Timer1 16-Bit Read/Write Mode

    206
  • 13.5 Timer1 Oscillator

    206
    • FIGURE 13-2: External Components for the Timer1 LP Oscillator

      206
    • TABLE 13-2: Capacitor Selection for the Timer Oscillator(2,3,4,5)

      206
    • 13.5.1 Using Timer1 as a Clock Source

      207
    • 13.5.2 Timer1 Oscillator Layout Considerations

      207
      • FIGURE 13-3: Oscillator Circuit with Grounded Guard Ring

        207
  • 13.6 Timer1 Interrupt

    207
  • 13.7 Resetting Timer1 Using the ECCP Special Event Trigger

    208
  • 13.8 Timer1 Gate

    208
    • 13.8.1 TIMER1 GATE COUNT ENABLE

      208
      • TABLE 13-3: TIMER1 GATE ENABLE SELECTIONS

        208
      • FIGURE 13-4: Timer1 Gate Count Enable Mode

        209
    • 13.8.2 TIMER1 GATE SOURCE SELECTION

      209
      • TABLE 13-4: TIMER1 GATE SOURCES

        209
    • 13.8.3 TIMER1 GATE TOGGLE MODE

      210
      • FIGURE 13-5: Timer1 Gate Toggle Mode

        210
    • 13.8.4 TIMER1 GATE SINGLE PULSE MODE

      211
    • 13.8.5 TIMER1 GATE VALUE STATUS

      211
      • FIGURE 13-6: Timer1 Gate Single Pulse Mode

        211
      • FIGURE 13-7: Timer1 Gate Single Pulse and Toggle Combined Mode

        212
      • TABLE 13-5: Registers Associated with Timer1 as a Timer/Counter

        212
• 14.0 Timer2 Module

  213
  • 14.1 Timer2 Operation

    213
    • Register 14-1: T2CON: Timer2 Control Register (Access FCAh)

      213
  • 14.2 Timer2 Interrupt

    214
  • 14.3 Timer2 Output

    214
    • FIGURE 14-1: Timer2 Block Diagram

      214
    • TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter

      214
• 15.0 Timer3 Module

  215
  • Register 15-1: T3CON: Timer3 Control Register (Access F79h)

    215
  • 15.1 Timer3 Gate Control Register

    216
    • Register 15-2: T3GCON: Timer3 Gate Control Register (Access F97h)(1)

      216
    • Register 15-3: TCLKCON: Timer clock control register (Banked F52h)

      217
  • 15.2 Timer3 Operation

    218
    • FIGURE 15-1: Timer3 Block Diagram

      218
  • 15.3 Timer3 16-Bit Read/Write Mode

    219
  • 15.4 Using the Timer1 Oscillator as the Timer3 Clock Source

    219
  • 15.5 Timer3 Gate

    219
    • 15.5.1 TIMER3 GATE COUNT ENABLE

      219
      • TABLE 15-1: TIMER3 GATE ENABLE SELECTIONS

        219
      • FIGURE 15-2: Timer3 Gate Count Enable Mode

        219
    • 15.5.2 TIMER3 GATE SOURCE SELECTION

      220
      • TABLE 15-2: TIMER3 GATE SOURCES

        220
    • 15.5.3 TIMER3 GATE TOGGLE MODE

      220
      • FIGURE 15-3: Timer3 Gate Toggle Mode

        220
    • 15.5.4 TIMER3 GATE SINGLE PULSE MODE

      221
      • FIGURE 15-4: Timer3 Gate Single Pulse Mode

        221
      • FIGURE 15-5: Timer3 Gate Single Pulse and Toggle Combined Mode

        222
    • 15.5.5 TIMER3 GATE VALUE STATUS

      222
    • 15.5.6 TIMER3 GATE EVENT INTERRUPT

      222
  • 15.6 Timer3 Interrupt

    223
  • 15.7 Resetting Timer3 Using the ECCP Special Event Trigger

    223
    • TABLE 15-3: Registers Associated with Timer3 as a Timer/Counter

      223
• 16.0 Timer4 Module

  225
  • 16.1 Timer4 Operation

    225
    • Register 16-1: T4CON: Timer4 Control Register (Access F76h)

      225
  • 16.2 Timer4 Interrupt

    226
  • 16.3 Output of TMR4

    226
    • FIGURE 16-1: Timer4 Block Diagram

      226
    • TABLE 16-1: Registers Associated with Timer4 as a Timer/Counter

      226
• 17.0 Real-Time Clock and Calendar (RTCC)

  227
  • FIGURE 17-1: RTCC Block Diagram

    227
  • 17.1 RTCC Module Registers

    228
  • RTCC Control Registers

    228
  • RTCC Value Registers

    228
  • Alarm Value Registers

    228
    • 17.1.1 RTCC Control Registers

      229
      • Register 17-1: RTCCFG: RTCC Configuration Register (Banked F3Fh)(1)

        229
      • Register 17-2: RTCCAL: RTCC Calibration Register (Banked F3Eh)

        230
      • Register 17-3: PADCFG1: Pad Configuration Register (Banked F3Ch)

        230
      • Register 17-4: ALRMCFG: Alarm Configuration Register (Access F91h)

        231
      • Register 17-5: ALRMRPT: Alarm Repeat Counter (Access F90h)

        232
    • 17.1.2 RTCVALH and RTCVALL Register Mappings

      233
      • Register 17-6: Reserved Register (Access F99h, PTR 11b)

        233
      • Register 17-7: Year: Year Value Register (Access F98h, PTR 11b)(1)

        233
      • Register 17-8: MONTH: Month Value Register (Access F99h, PTR 10b)(1)

        233
      • Register 17-9: DAY: Day Value Register (Access F98h, PTR 10b)(1)

        234
      • Register 17-10: WKDY: Weekday Value Register (Access F99h, PTR 01b)(1)

        234
      • Register 17-11: HOURS: Hours Value Register (Access F98h, PTR 01b)(1)

        235
      • Register 17-12: MINUTES: Minutes Value Register (Access F99h, PTR 00b)

        235
      • Register 17-13: SECONDS: Seconds Value Register (Access F98h, PTR 00b)

        235
    • 17.1.3 ALRMVALH and ALRMVALL Register Mappings

      236
      • Register 17-14: ALRMMNTH: Alarm Month Value Register (Access F8Fh, PTR 10b)(1)

        236
      • Register 17-15: ALRMDAY: Alarm Day Value Register (Access F8Eh, PTR 10b)(1)

        236
      • Register 17-16: ALRMWd: Alarm Weekday Value Register (Access F8Fh, PTR 01b)(1)

        237
      • Register 17-17: ALRMHr: Alarm Hours Value Register (Access F8Eh, PTR 01b)(1)

        237
      • Register 17-18: ALRMMIN: Alarm Minutes Value Register (Access F8Fh, PTR 00b)

        238
      • Register 17-19: ALRMSEC: Alarm Seconds Value Register (Access F8Eh, PTR 00b)

        238
    • 17.1.4 RTCEN Bit Write

      239
  • 17.2 Operation

    239
    • 17.2.1 Register Interface

      239
      • FIGURE 17-2: Timer Digit Format

        239
      • FIGURE 17-3: Alarm Digit Format

        239
    • 17.2.2 Clock Source

      240
      • FIGURE 17-4: Clock Source Multiplexing

        240
    • 17.2.3 Digit Carry Rules

      240
      • TABLE 17-1: Day of Week Schedule

        240
      • TABLE 17-2: Day to Month Rollover Schedule

        241
    • 17.2.4 Leap Year

      241
    • 17.2.5 General Functionality

      241
    • 17.2.6 Safety Window for Register Reads and Writes

      241
    • 17.2.7 Write Lock

      241
      • EXAMPLE 17-1: Setting the RTCWREN Bit

        241
    • 17.2.8 Register Mapping

      241
      • TABLE 17-3: RTCVALH and RTCVALL Register Mapping

        242
      • TABLE 17-4: ALRMVAL Register Mapping

        242
    • 17.2.9 Calibration

      242
      • EQUATION 17-1: Converting Error Clock Pulses

        242
  • 17.3 Alarm

    243
    • 17.3.1 Configuring the Alarm

      243
      • FIGURE 17-5: Alarm Mask Settings

        243
    • 17.3.2 Alarm Interrupt

      244
      • FIGURE 17-6: Timer Pulse Generation

        244
  • 17.4 Low-Power Modes

    244
  • 17.5 Reset

    244
    • 17.5.1 Device Reset

      244
    • 17.5.2 Power-on Reset (POR)

      244
  • 17.6 Register Maps

    245
    • TABLE 17-5: RTCC Control Registers

      245
    • TABLE 17-6: RTCC Value Registers

      245
    • TABLE 17-7: Alarm Value Registers

      245
• 18.0 Enhanced Capture/Compare/PWM (ECCP) Module

  247
  • Register 18-1: CCPxCON: ECCPx Control (Access FBAh/FB4h)

    248
  • 18.1 ECCP Outputs and Configuration

    249
    • 18.1.1 ECCP Module and Timer Resources

      249
      • TABLE 18-1: ECCP Mode – Timer Resource

        249
  • 18.2 Capture Mode

    249
    • 18.2.1 ECCP Pin Configuration

      249
    • 18.2.2 Timer1/Timer3 Mode Selection

      249
    • 18.2.3 Software Interrupt

      249
    • 18.2.4 ECCP Prescaler

      250
      • EXAMPLE 18-1: Changing Between Capture Prescalers

        250
      • FIGURE 18-1: Capture Mode Operation Block Diagram

        250
  • 18.3 Compare Mode

    251
    • 18.3.1 ECCP Pin Configuration

      251
    • 18.3.2 Timer1/Timer3 Mode Selection

      251
    • 18.3.3 Software Interrupt Mode

      251
    • 18.3.4 Special Event Trigger

      251
      • FIGURE 18-2: Compare Mode Operation Block Diagram

        251
  • 18.4 PWM Mode

    252
    • FIGURE 18-3: Simplified PWM Block Diagram

      252
    • FIGURE 18-4: PWM Output

      252
    • 18.4.1 PWM Period

      252
      • EQUATION 18-1:

        252
    • 18.4.2 PWM Duty Cycle

      252
      • EQUATION 18-2:

        252
      • EQUATION 18-3:

        253
    • 18.4.3 Setup for PWM Operation

      253
      • TABLE 18-2: Example PWM Frequencies and Resolutions at 40 MHz

        253
      • TABLE 18-3: Registers Associated with PWM, Timer2 and Timer4

        254
  • 18.5 PWM (Enhanced Mode)

    255
    • FIGURE 18-5: Example Simplified Block Diagram of the Enhanced PWM Mode

      255
    • TABLE 18-4: Example Pin Assignments for Various PWM Enhanced Modes

      256
    • FIGURE 18-6: Example PWM (enhanced Mode) Output Relationships (Active-High State)

      256
    • FIGURE 18-7: Example Enhanced PWM Output Relationships (Active-Low State)

      257
    • 18.5.1 Half-Bridge Mode

      258
      • FIGURE 18-8: Example of Half-Bridge PWM Output

        258
      • FIGURE 18-9: Example of Half-Bridge Applications

        258
    • 18.5.2 Full-Bridge Mode

      259
      • FIGURE 18-10: Example of Full-Bridge Application

        259
      • FIGURE 18-11: Example of Full-Bridge PWM Output

        260
      • FIGURE 18-12: Example of PWM Direction Change

        261
      • FIGURE 18-13: Example of PWM Direction Change at Near 100% Duty Cycle

        262
    • 18.5.3 Start-up Considerations

      262
    • 18.5.4 Enhanced PWM Auto-shutdown mode

      263
      • Register 18-2: ECCPxAS: ECCPx Auto-Shutdown Control Register (Access FBEh/FB8h)

        263
      • FIGURE 18-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        264
    • 18.5.5 Auto-Restart Mode

      264
      • FIGURE 18-15: PWM Auto-shutdown With Auto-Restart Enabled (PxRSEN = 1)

        264
    • 18.5.6 Programmable Dead-Band Delay Mode

      265
      • FIGURE 18-16: Example of Half-Bridge PWM Output

        265
      • FIGURE 18-17: Example of Half-Bridge Applications

        265
      • Register 18-3: ECCPxDEL: Enhanced PWM Control Register (Access FBDh/FB7h)

        266
    • 18.5.7 Pulse Steering Mode

      266
      • Register 18-4: PSTRxCON: Pulse Steering Control (Access FBFh/FB9h)(1)

        267
      • FIGURE 18-18: Simplified Steering Block Diagram

        268
      • FIGURE 18-19: Example of Steering Event at End of Instruction (STRSYNC = 0)

        268
      • FIGURE 18-20: Example of Steering Event at Beginning of Instruction (STRSYNC = 1)

        268
    • 18.5.8 Operation in Power-Managed Modes

      269
    • 18.5.9 Effects of a Reset

      269
      • TABLE 18-5: Registers Associated with ECCP1 Module and Timer1 to Timer3

        269
• 19.0 Master Synchronous Serial Port (MSSP) Module

  271
  • 19.1 Master SSP (MSSP) Module Overview

    271
  • 19.2 Control Registers

    272
  • 19.3 SPI Mode

    272
    • FIGURE 19-1: MSSPx Block Diagram (SPI Mode)

      272
    • 19.3.1 Registers

      273
      • Register 19-1: SSPxSTAT: MSSPx Status Register – SPI Mode (Access FC7h/F73h)

        273
      • Register 19-2: SSPxCON1: MSSPx Control Register 1 – SPI Mode (Access FC6h/F72h)

        274
    • 19.3.2 Operation

      275
    • 19.3.3 Open-Drain Output Option

      275
      • EXAMPLE 19-1: Loading the SSP1BUF (SSP1SR) Register

        275
    • 19.3.4 Enabling SPI I/O

      276
    • 19.3.5 Typical Connection

      276
      • FIGURE 19-2: SPI Master/Slave Connection

        276
    • 19.3.6 Master Mode

      277
      • FIGURE 19-3: SPI Mode Waveform (Master Mode)

        277
    • 19.3.7 Slave Mode

      278
    • 19.3.8 Slave Select Synchronization

      278
      • FIGURE 19-4: Slave Synchronization Waveform

        278
      • FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0)

        279
      • FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1)

        279
    • 19.3.9 Operation in Power-Managed Modes

      280
    • 19.3.10 Effects of a Reset

      280
    • 19.3.11 Bus Mode Compatibility

      280
      • TABLE 19-1: SPI Bus Modes

        280
    • 19.3.12 SPI Clock Speed and Module Interactions

      280
      • TABLE 19-2: Registers Associated with SPI Operation

        281
  • 19.4 SPI DMA Module

    282
    • 19.4.1 I/O PIN CONSIDERATIONS

      282
    • 19.4.2 RAM TO RAM COPY OPERATIONS

      282
    • 19.4.3 IDLE AND SLEEP CONSIDERATIONS

      282
    • 19.4.4 REGISTERS

      282
      • Register 19-3: DMACON1: DMA Control Register 1 (Access F88h)

        284
      • Register 19-4: DMACON2: DMA Control Register 2 (Access F86h)

        285
      • EQUATION 19-1: BYTES TRANSMITTED FOR A GIVEN DMABC

        287
    • 19.4.5 INTERRUPTS

      287
    • 19.4.6 Using the SPI DMA Module

      288
      • EXAMPLE 19-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER

        289
  • 19.5 I2C Mode

    291
    • FIGURE 19-7: MSSPx Block Diagram (I2C™ Mode)

      291
    • 19.5.1 Registers

      291
      • Register 19-5: SSPxSTAT: MSSPx Status Register – I2C™ Mode (Access FC7h/F73h)

        292
      • Register 19-6: SSPxCON1: MSSPx Control Register 1 – I2C™ Mode (Access FC6h/F72h)

        293
      • Register 19-7: SSPxCON2: MSSPx Control Register 2 –I2C™ Master Mode (Access FC5h/F71h)

        294
      • Register 19-8: SSPxCON2: MSSPx Control Register 2 – I2C™ Slave Mode (Access FC5h/F71h)

        295
      • Register 19-9: SSPxMSK: I2C™ Slave Address Mask Register – 7-bit Masking Mode (Access FC8h/F74h)(1)

        295
    • 19.5.2 Operation

      296
    • 19.5.3 Slave Mode

      296
      • EXAMPLE 19-3: Address Masking Examples in 5-bit Masking Mode

        297
      • EXAMPLE 19-4: Address Masking Examples in 7-Bit Masking Mode

        298
      • FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)

        300
      • FIGURE 19-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)

        301
      • FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)

        302
      • FIGURE 19-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)

        303
      • FIGURE 19-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)

        304
      • FIGURE 19-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)

        305
    • 19.5.4 Clock Stretching

      306
      • FIGURE 19-14: Clock Synchronization Timing

        307
      • FIGURE 19-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)

        308
      • FIGURE 19-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)

        309
    • 19.5.5 General Call Address Support

      310
      • FIGURE 19-17: Slave Mode General Call Address Sequence (7-Bit or 10-bit Addressing Mode)

        310
    • 19.5.6 Master Mode

      310
      • FIGURE 19-18: MSSPx Block Diagram (I2C™ Master Mode)

        311
    • 19.5.7 Baud Rate

      312
      • FIGURE 19-19: Baud Rate Generator Block Diagram

        313
      • TABLE 19-3: I2C™ Clock Rate w/BRG

        313
      • FIGURE 19-20: Baud Rate Generator Timing with Clock Arbitration

        314
    • 19.5.8 I2C Master Mode Start Condition Timing

      314
      • FIGURE 19-21: First Start Bit Timing

        314
    • 19.5.9 I2C Master Mode Repeated Start Condition Timing

      315
      • FIGURE 19-22: Repeated Start Condition Waveform

        315
    • 19.5.10 I2C Master Mode Transmission

      316
    • 19.5.11 I2C Master Mode Reception

      316
      • FIGURE 19-23: I2C™ Master Mode Waveform (Transmission, 7-Bit or 10-bit Address)

        317
      • FIGURE 19-24: I2C™ Master Mode Waveform (Reception, 7-bit Address)

        318
    • 19.5.12 Acknowledge Sequence Timing

      319
    • 19.5.13 Stop Condition Timing

      319
      • FIGURE 19-25: Acknowledge Sequence Waveform

        319
      • FIGURE 19-26: Stop Condition Receive or Transmit Mode

        319
    • 19.5.14 Sleep Operation

      320
    • 19.5.15 Effects of a Reset

      320
    • 19.5.16 Multi-master Mode

      320
    • 19.5.17 Multi -master Communication, Bus Collision and Bus Arbitration

      320
      • FIGURE 19-27: Bus Collision Timing for Transmit and Acknowledge

        320
      • FIGURE 19-28: Bus Collision During Start Condition (SDAx Only)

        321
      • FIGURE 19-29: Bus Collision During Start Condition (SCLx = 0)

        322
      • FIGURE 19-30: BRG Reset Due to SDAx Arbitration During Start Condition

        322
      • FIGURE 19-31: Bus Collision During a Repeated Start Condition (Case 1)

        323
      • FIGURE 19-32: Bus Collision During Repeated Start Condition (Case 2)

        323
      • FIGURE 19-33: Bus Collision During a Stop Condition (Case 1)

        324
      • FIGURE 19-34: Bus Collision During a Stop Condition (Case 2)

        324
      • TABLE 19-4: Registers Associated with I2C™ Operation

        325
• 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  327
  • Register 20-1: TXSTAx: Transmit Status And Control Register (Access FADh/FA8h)

    328
  • Register 20-2: RCSTAx: Receive Status And Control Register (Access FACh/F9Ch)

    329
  • Register 20-3: BAUDCONx: Baud Rate Control Register (Access F7Eh/F7Ch)

    330
  • 20.1 Baud Rate Generator (BRG)

    331
    • 20.1.1 Operation in Power-Managed Modes

      331
    • 20.1.2 Sampling

      331
      • TABLE 20-1: Baud Rate Formulas

        331
      • EXAMPLE 20-1: Calculating Baud Rate Error

        332
      • TABLE 20-2: Registers Associated with Baud Rate Generator

        332
      • TABLE 20-3: Baud Rates for Asynchronous Modes

        333
    • 20.1.3 Auto-Baud Rate Detect

      335
      • TABLE 20-4: BRG Counter Clock Rates

        335
      • FIGURE 20-1: Automatic Baud Rate Calculation

        336
      • FIGURE 20-2: BRG Overflow Sequence

        336
  • 20.2 EUSART Asynchronous Mode

    337
    • 20.2.1 EUSART Asynchronous Transmitter

      337
      • FIGURE 20-3: EUSART Transmit Block Diagram

        337
      • FIGURE 20-4: Asynchronous Transmission

        338
      • FIGURE 20-5: Asynchronous Transmission (Back-to-Back)

        338
      • TABLE 20-5: Registers Associated with Asynchronous Transmission

        338
    • 20.2.2 EUSART Asynchronous Receiver

      339
    • 20.2.3 Setting Up 9-bit Mode with Address Detect

      339
      • FIGURE 20-6: EUSARTx Receive Block Diagram

        340
      • FIGURE 20-7: Asynchronous Reception

        340
      • TABLE 20-6: Registers Associated with Asynchronous Reception

        341
    • 20.2.4 Auto-Wake-up on Sync Break Character

      341
      • FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation

        342
      • FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep

        342
    • 20.2.5 Break Character Sequence

      343
    • 20.2.6 Receiving A Break Character

      343
      • FIGURE 20-10: Send Break Character Sequence

        343
  • 20.3 EUSART Synchronous Master Mode

    344
    • 20.3.1 EUSART Synchronous Master Transmission

      344
      • FIGURE 20-11: Synchronous Transmission

        344
      • FIGURE 20-12: Synchronous Transmission (Through TXEN)

        345
      • TABLE 20-7: Registers Associated with Synchronous Master Transmission

        345
    • 20.3.2 EUSART Synchronous Master Reception

      346
      • FIGURE 20-13: Synchronous Reception (Master Mode, SREN)

        346
      • TABLE 20-8: Registers Associated with Synchronous Master Reception

        347
  • 20.4 EUSART Synchronous Slave Mode

    348
    • 20.4.1 EUSART Synchronous Slave Transmission

      348
      • TABLE 20-9: Registers Associated with Synchronous Slave Transmission

        349
    • 20.4.2 EUSART Synchronous Slave Reception

      350
      • TABLE 20-10: Registers Associated with Synchronous Slave Reception

        350
• 21.0 10-bit Analog-to-Digital Converter (A/D) Module

  351
  • Register 21-1: ADCON0: A/D Control Register 0 (Access FC2h)

    351
  • Register 21-2: ADCON1: A/D Control Register 1 (Access FC1h)

    352
  • Register 21-3: ANCON0: A/D Port Configuration Register 2 (Banked F48h)

    353
  • Register 21-4: ANCON1: A/D Port Configuration Register 1 (Banked F49h)

    353
  • FIGURE 21-1: A/D Block Diagram

    354
  • FIGURE 21-2: Analog Input Model

    355
  • 21.1 A/D Acquisition Requirements

    356
    • EQUATION 21-1: Acquisition Time

      356
    • EQUATION 21-2: A/D Minimum Charging Time

      356
    • EQUATION 21-3: Calculating the Minimum Required Acquisition Time

      356
  • 21.2 Selecting and Configuring Automatic Acquisition Time

    357
  • 21.3 Selecting the A/D Conversion Clock

    357
    • TABLE 21-1: Tad vs. Device Operating Frequencies

      357
  • 21.4 Configuring Analog Port Pins

    357
  • 21.5 A/D Conversions

    358
  • 21.6 Use of the ECCP2 Trigger

    358
    • FIGURE 21-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)

      358
    • FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)

      358
  • 21.7 A/D Converter Calibration

    359
  • 21.8 Operation in Power-Managed Modes

    359
    • EXAMPLE 21-1: Sample A/D Calibration Routine

      359
    • TABLE 21-2: Summary of A/D Registers

      360
• 22.0 Comparator Module

  361
  • 22.1 Registers

    361
    • FIGURE 22-1: Comparator Simplified Block Diagram

      361
    • Register 22-1: CMxCON: Comparator Control x Register (Access FD2h/FD1h)

      362
    • Register 22-2: CMSTAT: Comparator Status Register (Access F70h)

      363
  • 22.2 Comparator Operation

    364
    • FIGURE 22-2: Single Comparator

      364
  • 22.3 Comparator Response Time

    364
  • 22.4 Analog Input Connection Considerations

    364
    • FIGURE 22-3: Comparator Analog Input Model

      364
  • 22.5 Comparator Control and Configuration

    365
    • TABLE 22-1: Comparator Inputs and Outputs

      365
    • 22.5.1 Comparator Enable and Input selection

      365
    • 22.5.2 Comparator Enable and OUtput Selection

      365
      • FIGURE 22-4: Comparator Configurations

        366
  • 22.6 Comparator Interrupts

    367
    • TABLE 22-2: Comparator Interrupt Generation

      367
  • 22.7 Comparator Operation During Sleep

    368
  • 22.8 Effects of a Reset

    368
    • TABLE 22-3: Registers Associated with Comparator Module

      368
• 23.0 Comparator Voltage Reference Module

  369
  • FIGURE 23-1: Comparator Voltage Reference Block Diagram

    369
  • 23.1 Configuring the Comparator Voltage Reference

    370
    • EQUATION 23-1: Calculating Output of the Comparator Voltage Reference

      370
    • Register 23-1: CVRCON: Comparator Voltage Reference Control Register (Banked F53h)

      370
  • 23.2 Voltage Reference Accuracy/Error

    371
  • 23.3 Connection Considerations

    371
  • 23.4 Operation During Sleep

    371
  • 23.5 Effects of a Reset

    371
    • FIGURE 23-2: Comparator Voltage Reference Output Buffer Example

      371
    • TABLE 23-1: Registers Associated with Comparator Voltage Reference

      371
• 24.0 High/Low Voltage Detect (HLVD)

  373
  • Register 24-1: HLVDCON: High/Low-Voltage Detect Control Register (Access F85h)

    373
  • 24.1 Operation

    374
    • FIGURE 24-1: HLVD Module Block Diagram (with External Input)

      374
  • 24.2 HLVD Setup

    375
  • 24.3 Current Consumption

    375
  • 24.4 HLVD Start-up Time

    375
    • FIGURE 24-2: Low-Voltage Detect Operation (VDIRMAG = 0)

      376
    • FIGURE 24-3: High-Voltage Detect Operation (VDIRMAG = 1)

      377
  • 24.5 Applications

    377
    • FIGURE 24-4: Typical High/ Low-Voltage Detect Application

      377
  • 24.6 Operation During Sleep

    378
  • 24.7 Effects of a Reset

    378
    • TABLE 24-1: Registers Associated with High/Low-Voltage Detect Module

      378
• 25.0 Charge Time Measurement Unit (CTMU)

  379
  • FIGURE 25-1: CTMU Block Diagram

    379
  • 25.1 CTMU Operation

    380
    • 25.1.1 Theory of Operation

      380
    • 25.1.2 Current Source

      380
    • 25.1.3 Edge Selection and Control

      380
    • 25.1.4 Edge Status

      380
    • 25.1.5 Interrupts

      381
  • 25.2 CTMU Module Initialization

    381
  • 25.3 Calibrating the CTMU Module

    381
    • 25.3.1 Current Source Calibration

      381
      • FIGURE 25-2: CTMU Current Source Calibration Circuit

        382
      • EXAMPLE 25-1: Setup for CTMU Calibration Routines

        383
      • EXAMPLE 25-2: Current Calibration Routine

        384
    • 25.3.2 Capacitance Calibration

      385
      • EXAMPLE 25-3: Capacitance Calibration Routine

        386
  • 25.4 Measuring Capacitance with the CTMU

    387
    • 25.4.1 Absolute Capacitance Measurement

      387
    • 25.4.2 Relative Charge Measurement

      387
      • EXAMPLE 25-4: Routine for Capacitive Touch Switch

        388
  • 25.5 Measuring Time with the CTMU Module

    389
    • FIGURE 25-3: Typical Connections and Internal Configuration for Time Measurement

      389
  • 25.6 Creating a Delay with the CTMU Module

    390
    • FIGURE 25-4: Typical Connections and Internal Configuration for Pulse Delay Generation

      390
  • 25.7 Operation During Sleep/Idle Modes

    390
    • 25.7.1 Sleep Mode and Deep Sleep Modes

      390
    • 25.7.2 Idle Mode

      390
  • 25.8 Effects of a Reset on CTMU

    390
  • 25.9 Registers

    391
    • Register 25-1: CTMUCONH: CTMU Control Register High (Access FB3h)

      391
    • Register 25-2: CTMUCONL: CTMU Control Register Low (Access FB2h)

      392
    • Register 25-3: CTMUICON: CTMU current Control Register (Access FB1h)

      393
    • TABLE 25-1: Registers Associated with CTMU Module

      393
• 26.0 Special Features of the CPU

  395
  • 26.1 Configuration Bits

    395
    • 26.1.1 Considerations for Configuring the PIC18F46J11 family Devices

      395
      • TABLE 26-1: Mapping of the Flash Configuration Words to the Configuration Registers

        396
      • TABLE 26-2: Configuration Bits and Device IDs

        396
      • Register 26-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)

        397
      • Register 26-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)

        398
      • Register 26-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)

        399
      • Register 26-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)

        400
      • Register 26-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)

        401
      • Register 26-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)

        402
      • Register 26-7: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)

        402
      • Register 26-8: CONFIG4H: Configuration Register 4 High (Byte Address 300007h)

        403
      • Register 26-9: DEVID1: Device ID Register 1 for PIC18F46J11 family Devices (Byte Address 3FFFFEh)

        403
      • Register 26-10: DEVID2: Device ID Register 2 for PIC18F46J11 family Devices (Byte Address 3FFFFFh)

        404
  • 26.2 Watchdog Timer (WDT)

    405
    • 26.2.1 Control Register

      405
      • FIGURE 26-1: WDT Block Diagram

        405
      • Register 26-11: WDTCON: Watchdog Timer Control Register (Access FC0h)

        406
      • TABLE 26-3: Summary of Watchdog Timer Registers

        406
  • 26.3 On-Chip Voltage Regulator

    407
    • 26.3.1 Voltage Regulator Tracking Mode And Low-Voltage Detection

      407
      • FIGURE 26-2: Connections for the On-Chip Regulator

        408
    • 26.3.2 On-Chip Regulator and BOR

      408
    • 26.3.3 Power-up Requirements

      408
    • 26.3.4 OPERATION IN SLEEP MODE

      408
  • 26.4 Two-Speed Start-up

    409
    • FIGURE 26-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)

      409
    • 26.4.1 Special Considerations for Using Two-Speed Start-up

      409
  • 26.5 Fail-Safe Clock Monitor

    409
    • FIGURE 26-4: FSCM Block Diagram

      410
    • 26.5.1 FSCM and the Watchdog Timer

      410
      • FIGURE 26-5: FSCM Timing Diagram

        410
    • 26.5.2 Exiting Fail-Safe Operation

      411
    • 26.5.3 FSCM Interrupts in Power-Managed Modes

      411
    • 26.5.4 POR or Wake-up From Sleep

      411
  • 26.6 Program Verification and Code Protection

    411
    • 26.6.1 Configuration Register Protection

      411
  • 26.7 In-Circuit Serial Programming (ICSP)

    412
  • 26.8 In-Circuit Debugger

    412
    • TABLE 26-4: Debugger Resources

      412
• 27.0 Instruction Set Summary

  413
  • 27.1 Standard Instruction Set

    413
    • TABLE 27-1: Opcode Field Descriptions

      414
    • EXAMPLE 27-1: General Format for Instructions

      415
    • TABLE 27-2: PIC18F46J11 family Instruction Set

      416
    • 27.1.1 Standard Instruction Set

      419
  • 27.2 Extended Instruction Set

    455
    • 27.2.1 Extended Instruction Syntax

      455
      • TABLE 27-3: Extensions to the PIC18 Instruction Set

        455
    • 27.2.2 Extended Instruction Set

      456
    • 27.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      460
    • 27.2.4 Considerations When Enabling the Extended Instruction Set

      460
    • 27.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      462
• 28.0 Development Support

  463
  • 28.1 MPLAB Integrated Development Environment Software

    463
  • 28.2 MPASM Assembler

    464
  • 28.3 MPLAB C18 and MPLAB C30 C Compilers

    464
  • 28.4 MPLINK Object Linker/ MPLIB Object Librarian

    464
  • 28.5 MPLAB ASM30 Assembler, Linker and Librarian

    464
  • 28.6 MPLAB SIM Software Simulator

    464
  • 28.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator

    465
  • 28.8 MPLAB REAL ICE In-Circuit Emulator System

    465
  • 28.9 MPLAB ICD 2 In-Circuit Debugger

    465
  • 28.10 MPLAB PM3 Device Programmer

    465
  • 28.11 PICSTART Plus Development Programmer

    466
  • 28.12 PICkit 2 Development Programmer

    466
  • 28.13 Demonstration, Development and Evaluation Boards

    466
• 29.0 Electrical Characteristics

  467
  • Absolute Maximum Ratings(†)

    467
    • FIGURE 29-1: PIC18F46J11 family Vdd frequency Graph (Industrial)

      467
    • FIGURE 29-2: PIC18LF46J11 Vddcore frequency Graph (Industrial)(1)

      468
  • 29.1 DC Characteristics: Supply Voltage PIC18F46J11 Family (Industrial)

    469
  • 29.2 DC Characteristics: Power-Down and Supply Current PIC18F46J11 Family (Industrial)

    470
  • 29.3 DC Characteristics: PIC18F46J11 Family (Industrial)

    480
    • TABLE 29-1: Memory Programming Requirements

      482
    • TABLE 29-2: Comparator Specifications

      482
    • TABLE 29-3: CTMU Current Source Specifications

      482
    • TABLE 29-4: Voltage Reference Specifications

      482
    • TABLE 29-5: Internal Voltage Regulator Specifications

      483
    • TABLE 29-6: ULPWU Specifications

      483
    • FIGURE 29-3: High/Low-Voltage Detect Characteristics

      484
    • TABLE 29-7: High/Low-Voltage Detect Characteristics

      484
  • 29.4 AC (Timing) Characteristics

    485
    • 29.4.1 Timing Parameter Symbology

      485
    • 29.4.2 Timing Conditions

      486
      • TABLE 29-8: Temperature and Voltage Specifications – AC

        486
      • FIGURE 29-4: Load Conditions for Device Timing Specifications

        486
    • 29.4.3 Timing Diagrams and Specifications

      486
      • FIGURE 29-5: External Clock Timing

        486
      • TABLE 29-9: External Clock Timing Requirements

        487
      • TABLE 29-10: PLL Clock Timing Specifications

        487
      • TABLE 29-11: Internal RC Accuracy (INTOSC and INTRC Sources)

        487
      • FIGURE 29-6: CLKO and I/O Timing

        488
      • TABLE 29-12: CLKO and I/O Timing Requirements

        488
      • FIGURE 29-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        489
      • TABLE 29-13: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        489
      • TABLE 29-14: Low-Power Wake-Up Time

        490
      • FIGURE 29-8: Timer0 and Timer1 External Clock Timings

        491
      • TABLE 29-15: Timer0 and Timer1 External Clock Requirements

        491
      • FIGURE 29-9: Enhanced Capture/Compare/PWM Timings

        492
      • TABLE 29-16: Enhanced Capture/Compare/PWM Requirements

        492
      • FIGURE 29-10: Parallel Master Port Read Timing Diagram

        493
      • TABLE 29-17: Parallel Master Port Read Timing Requirements

        493
      • FIGURE 29-11: Parallel Master Port Write Timing Diagram

        494
      • TABLE 29-18: Parallel Master Port Write Timing Requirements

        494
      • FIGURE 29-12: Parallel Slave Port Timing

        495
      • TABLE 29-19: Parallel Slave Port Requirements

        495
      • FIGURE 29-13: Example SPI Master Mode Timing (CKE = 0)

        496
      • TABLE 29-20: Example SPI Mode Requirements (Master Mode, Cke = 0)

        496
      • FIGURE 29-14: Example SPI Master Mode Timing (CKE = 1)

        497
      • TABLE 29-21: Example SPI Mode Requirements (Master Mode, CKE = 1)

        497
      • FIGURE 29-15: Example SPI Slave Mode Timing (CKE = 0)

        498
      • TABLE 29-22: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)

        498
      • FIGURE 29-16: Example SPI Slave Mode Timing (CKE = 1)

        499
      • TABLE 29-23: Example SPI Slave Mode Requirements (CKE = 1)

        499
      • FIGURE 29-17: I2C™ Bus Start/Stop Bits Timing

        500
      • TABLE 29-24: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        500
      • FIGURE 29-18: I2C™ Bus Data Timing

        500
      • TABLE 29-25: I2C™ Bus Data Requirements (Slave Mode)

        501
      • FIGURE 29-19: MSSPx I2C™ Bus Start/Stop Bits Timing Waveforms

        502
      • TABLE 29-26: MSSPx I2C™ Bus Start/Stop Bits Requirements

        502
      • FIGURE 29-20: MSSPx I2C™ Bus Data Timing

        502
      • TABLE 29-27: MSSPx I2C™ Bus Data Requirements

        503
      • FIGURE 29-21: EUSARTx Synchronous Transmission (Master/Slave) Timing

        504
      • TABLE 29-28: EUSARTx Synchronous Transmission Requirements

        504
      • FIGURE 29-22: EUSARTx Synchronous Receive (Master/Slave) Timing

        504
      • TABLE 29-29: EUSARTx Synchronous Receive Requirements

        504
      • TABLE 29-30: A/D Converter Characteristics: PIC18F46J11 family (Industrial)

        505
      • FIGURE 29-23: A/D Conversion Timing

        506
      • TABLE 29-31: A/D Conversion Requirements

        506
• 30.0 Packaging Information

  507
  • 30.1 Package Marking Information

    507
  • 30.2 Package Details

    509
• Appendix A: Revision History

  519
• Appendix B: Device Differences

  519
  • TABLE B-1: DEVICE DIFFERENCES BETWEEN PIC18F46J11 family MEMBERS

    519
• INDEX

  521
  • The Microchip Web Site

    533
  • Customer Change Notification Service

    533
  • Customer Support

    533
  • Reader Response

    534
• Product Identification System

  535
• Worldwide Sales and Service

  536