データシート目次Overview1TABLE 1: 100-Pin TQFP to 100-Pin PIM Pinout1FIGURE 1: 100-Pin Device Schematic4FIGURE 2: 100-Pin Socket Schematic5Trademarks7Worldwide Sales8サイズ： 199KBページ数： 8Language: Englishマニュアルを開く
データシート目次Operating Conditions1Core: 16-Bit dsPIC33F1Clock Management1Power Management1High-Speed PWM1Advanced Analog Features1Timers/Output Compare/Input Capture1Communication Interfaces1Direct Memory Access (DMA)1Input/Output1Qualification and Class B Support1Debugger Development Support1dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Product Families2TABLE 1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Controller Families2Pin Diagrams3Pin Diagrams (Continued)4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)10Pin Diagrams (Continued)11Pin Diagrams (Continued)12Table of Contents13Most Current Data Sheet14Errata14Customer Notification System14Referenced Sources151.0 Device Overview17FIGURE 1-1: Device Block Diagram18TABLE 1-1: Pinout I/O Descriptions192.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers232.1 Basic Connection Requirements232.2 Decoupling Capacitors23FIGURE 2-1: Recommended Minimum Connection242.2.1 Tank Capacitors242.3 Capacitor on Internal Voltage Regulator (Vcap)242.4 Master Clear (MCLR) Pin24FIGURE 2-2: Example of MCLR Pin Connections(1,2)242.5 ICSP Pins252.6 External Oscillator Pins25FIGURE 2-3: Suggested Placement of the Oscillator Circuit252.7 Oscillator Value Conditions on Device Start-up262.8 Configuration of Analog and Digital Pins During ICSP Operations262.9 Unused I/Os262.10 Typical Application Connection Examples26FIGURE 2-4: Digital PFC27FIGURE 2-5: Boost Converter Implementation27FIGURE 2-6: Single-Phase Synchronous Buck converter28FIGURE 2-7: Multiphase Synchronous Buck converter28FIGURE 2-8: Off-Line UPS29FIGURE 2-9: Interleaved PFC30FIGURE 2-10: Phase-Shifted Full-Bridge Converter31FIGURE 2-11: AC-to-DC Power Supply with PFC and Three Outputs (12V, 5V and 3.3V)323.0 CPU333.1 Data Addressing Overview333.2 DSP Engine Overview333.3 Special MCU Features34FIGURE 3-1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU Core Block Diagram34FIGURE 3-2: Programmer’s Model353.4 CPU Control Registers36Register 3-1: SR: CPU STATUS Register36Register 3-2: CORCON: CORE Control Register383.5 Arithmetic Logic Unit (ALU)393.5.1 Multiplier393.5.2 Divider393.6 DSP Engine39TABLE 3-1: DSP Instructions Summary39FIGURE 3-3: DSP Engine Block Diagram403.6.1 Multiplier413.6.2 Data Accumulators and Adder/Subtracter413.6.3 Accumulator ‘Write-Back’423.6.4 Barrel Shifter434.0 Memory Organization454.1 Program Address Space45FIGURE 4-1: Program Memory Maps for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Devices454.1.1 Program Memory Organization464.1.2 Interrupt and Trap Vectors46FIGURE 4-2: Program Memory Organization464.2 Data Address Space474.2.1 Data Space Width474.2.2 Data Memory Organization and Alignment474.2.3 SFR Space474.2.4 Near Data Space47FIGURE 4-3: Data Memory Map for Devices with 4-Kbyte RAM48FIGURE 4-4: Data Memory Map for Devices with 8-Kbyte RAM49FIGURE 4-5: Data Memory Map for Devices with 9-Kbyte RAM504.2.5 X and Y Data Spaces514.2.6 DMA RAM51TABLE 4-1: CPU Core Register Map52TABLE 4-2: Change Notification Register Map for dsPIC33FJ32GS608/610 and dsPIC33FJ64GS608/610 Devices54TABLE 4-3: Change Notification Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 Devices54TABLE 4-4: Interrupt Controller Register Map for dsPIC33FJ64GS610 Devices55TABLE 4-5: Interrupt Controller Register Map for dsPIC33FJ64GS608 Devices57TABLE 4-6: Interrupt Controller Register Map for dsPIC33FJ64GS606 Devices59TABLE 4-7: Interrupt Controller Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices61TABLE 4-8: Interrupt Controller Register Map for dsPIC33FJ32GS610 Devices63TABLE 4-9: Interrupt Controller Register Map for dsPIC33FJ32GS60865TABLE 4-10: Interrupt Controller Register Map for dsPIC33FJ32GS606 Devices67TABLE 4-11: Timers REGISTER MAP69TABLE 4-12: INPUT capture register map69TABLE 4-13: output compare register Map70TABLE 4-14: QEI1 Register Map70TABLE 4-15: QEI2 Register Map70TABLE 4-16: High-Speed pwm register map71TABLE 4-17: High-Speed pwm Generator 1 register map71TABLE 4-18: High-Speed pwm Generator 2 register map72TABLE 4-19: High-Speed pwm Generator 3 register Map73TABLE 4-20: High-Speed pwm Generator 4 register map74TABLE 4-21: High-Speed pwm Generator 5 register map75TABLE 4-22: High-Speed pwm Generator 6 register map76TABLE 4-23: High-Speed pwm Generator 7 register map (excludes dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices)77TABLE 4-24: High-Speed pwm Generator 8 register map (excludes dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices)78TABLE 4-25: High-Speed pwm Generator 9 register map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices79TABLE 4-26: i2c1 register map80TABLE 4-27: i2c2 register map80TABLE 4-28: uart1 register map81TABLE 4-29: UART2 Register Map81TABLE 4-30: spi1 register map82TABLE 4-31: spi2 register map82TABLE 4-32: High-Speed 10-Bit ADC Register Map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices Only83TABLE 4-33: High-Speed 10-Bit ADC Register Map for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices85TABLE 4-34: High-Speed 10-Bit ADC Register Map for dsPIC33FJ32GS606 and dsPIC33FJ64GS606 Devices86TABLE 4-35: High-Speed 10-Bit ADC Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices87TABLE 4-36: DMA Register Map88TABLE 4-37: ECAN1 Register Map When WIN (C1CTRL1<0>) = 0 or 189TABLE 4-38: ECAN1 Register Map When WIN (C1CTRL1<0>) = 089TABLE 4-39: ECAN1 Register Map When WIN (C1CTRL1<0>) = 190TABLE 4-40: Analog Comparator Control Register Map91TABLE 4-41: PORTA Register Map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices92TABLE 4-42: PORTA Register Map for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices92TABLE 4-43: PORTB Register Map92TABLE 4-44: PORTc Register Map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices92TABLE 4-45: PORTc Register Map for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices93TABLE 4-46: PORTc Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 Devices93TABLE 4-47: PORTD Register Map for dsPIC33FJ32GS608/610 and dsPIC33FJ64GS608/610 Devices93TABLE 4-48: PORTD Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 Devices93TABLE 4-49: PORTE Register Map for dsPIC33FJ32GS608/610 and dsPIC33FJ64GS608/610 Devices94TABLE 4-50: PORTE Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 Devices94TABLE 4-51: PORTF Register Map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices94TABLE 4-52: PORTF Register Map for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices94TABLE 4-53: PORTF Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 Devices95TABLE 4-54: PORTG Register Map for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 Devices95TABLE 4-55: PORTG Register Map for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 Devices95TABLE 4-56: PORTG Register Map for dsPIC33FJ32GS406/606 and dsPIC33FJ64GS406/606 Devices95TABLE 4-57: System Control Register Map96TABLE 4-58: NVM Register Map96TABLE 4-59: PMD Register Map for dsPIC33FJ64GS610 Devices96TABLE 4-60: PMD Register Map for dsPIC33FJ32GS610 Devices97TABLE 4-61: PMD Register Map for dsPIC33FJ64GS608 Devices97TABLE 4-62: PMD Register Map for dsPIC33FJ32GS608 Devices97TABLE 4-63: PMD Register Map for dsPIC33FJ64GS606 Devices98TABLE 4-64: PMD Register Map for dsPIC33FJ32GS606 Devices98TABLE 4-65: PMD Register Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices984.2.7 Software Stack99FIGURE 4-6: CALL Stack Frame994.3 Instruction Addressing Modes994.3.1 File Register Instructions994.3.2 MCU Instructions99TABLE 4-66: Fundamental Addressing Modes Supported1004.3.3 Move and Accumulator Instructions1004.3.4 MAC Instructions1004.3.5 Other Instructions1004.4 Modulo Addressing1014.4.1 Start and End Address1014.4.2 W Address Register Selection101FIGURE 4-7: Modulo Addressing Operation Example1014.4.3 Modulo Addressing Applicability1024.5 Bit-Reversed Addressing1024.5.1 Bit-Reversed Addressing Implementation102FIGURE 4-8: Bit-Reversed Address Example103TABLE 4-67: Bit-Reversed Address Sequence (16-Entry)1034.6 Interfacing Program and Data Memory Spaces1044.6.1 Addressing Program Space104TABLE 4-68: Program Space Address Construction104FIGURE 4-9: Data Access from Program Space Address Generation1054.6.2 Data Access From Program Memory Using Table Instructions106FIGURE 4-10: Accessing Program Memory with Table Instructions1064.6.3 Reading Data from Program Memory Using Program Space Visibility107FIGURE 4-11: Program Space Visibility Operation1075.0 Flash Program Memory1095.1 Table Instructions and Flash Programming109FIGURE 5-1: Addressing for Table Registers1095.2 RTSP Operation1105.3 Programming Operations110EQUATION 5-1: Programming Time110EQUATION 5-2: Minimum Row Write Time110EQUATION 5-3: Maximum Row Write Time1105.4 Control Registers110Register 5-1: NVMCON: Flash Memory Control Register111Register 5-2: NVMKEY: Nonvolatile Memory Key Register1125.4.1 Programming Algorithm for Flash Program Memory113EXAMPLE 5-1: Erasing a Program Memory Page113EXAMPLE 5-2: Loading the Write Buffers114EXAMPLE 5-3: Initiating a Programming Sequence1146.0 Resets115FIGURE 6-1: Reset System Block Diagram116Register 6-1: RCON: Reset Control Register(1)1176.1 System Reset118TABLE 6-1: Oscillator Delay118FIGURE 6-2: System Reset Timing119TABLE 6-2: Oscillator Delay1196.2 Power-on Reset (POR)1206.3 Brown-out Reset (BOR) and Power-up Timer (PWRT)120FIGURE 6-3: Brown-out Situations1206.4 External Reset (EXTR)1216.4.1 External supervisory circuit1216.4.2 Internal Supervisory Circuit1216.5 Software RESET Instruction (SWR)1216.6 Watchdog Timer Time-out Reset (WDTO)1216.7 Trap Conflict Reset1216.8 Illegal Condition Device Reset1216.8.1 Illegal Opcode Reset1216.8.2 Uninitialized W Register Reset1216.8.3 Security Reset1216.9 Using the RCON Status Bits122TABLE 6-3: Reset Flag Bit Operation1227.0 Interrupt Controller1237.1 Interrupt Vector Table1237.1.1 Alternate Interrupt Vector Table1237.2 Reset Sequence123FIGURE 7-1: dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Interrupt Vector Table124TABLE 7-1: Interrupt Vectors1257.3 Interrupt Control and Status Registers1277.3.1 INTCON1 and INTCON21277.3.2 IFSx1277.3.3 IECx1277.3.4 IPCx1277.3.5 INTTREG1277.3.6 status/Control registers127Register 7-1: SR: CPU STATUS Register(1)128Register 7-2: CORCON: CORE Control Register(1)128Register 7-3: INTCON1: Interrupt Control Register 1129Register 7-4: INTCON2: Interrupt Control Register 2131Register 7-5: IFS0: Interrupt Flag Status Register 0132Register 7-6: IFS1: Interrupt Flag Status Register 1134Register 7-7: IFS2: Interrupt Flag Status Register 2136Register 7-8: IFS3: Interrupt Flag Status Register 3137Register 7-9: IFS4: Interrupt Flag Status Register 4138Register 7-10: IFS5: Interrupt Flag Status Register 5139Register 7-11: IFS6: Interrupt Flag Status Register 6140Register 7-12: IFS7: Interrupt Flag Status Register 7141Register 7-13: IEC0: Interrupt Enable Control Register 0142Register 7-14: IEC1: Interrupt Enable Control Register 1144Register 7-15: IEC2: Interrupt Enable Control Register 2146Register 7-16: IEC3: Interrupt Enable Control Register 3147Register 7-17: IEC4: Interrupt Enable Control Register 4148Register 7-18: IEC5: Interrupt Enable Control Register 5149Register 7-19: IEC6: Interrupt Enable Control Register 6150Register 7-20: IEC7: Interrupt Enable Control Register 7151Register 7-21: IPC0: Interrupt Priority Control Register 0152Register 7-22: IPC1: Interrupt Priority Control Register 1153Register 7-23: IPC2: Interrupt Priority Control Register 2154Register 7-24: IPC3: Interrupt Priority Control Register 3155Register 7-25: IPC4: Interrupt Priority Control Register 4156Register 7-26: IPC5: Interrupt Priority Control Register 5157Register 7-27: IPC6: Interrupt Priority Control Register 6158Register 7-28: IPC7: Interrupt Priority Control Register 7159Register 7-29: IPC8: Interrupt Priority Control Register 8160Register 7-30: IPC9: Interrupt Priority Control Register 9161Register 7-31: IPC12: Interrupt Priority Control Register 12162Register 7-32: IPC13: Interrupt Priority Control Register 13163Register 7-33: IPC14: Interrupt Priority Control Register 14164Register 7-34: IPC16: Interrupt Priority Control Register 16165Register 7-35: IPC17: Interrupt Priority Control Register 17166Register 7-36: IPC18: Interrupt Priority Control Register 18167Register 7-37: IPC20: Interrupt Priority Control Register 20168Register 7-38: IPC21: Interrupt Priority Control Register 21169Register 7-39: IPC23: Interrupt Priority Control Register 23170Register 7-40: IPC24: Interrupt Priority Control Register 24171Register 7-41: IPC25: Interrupt Priority Control Register 25172Register 7-42: IPC26: Interrupt Priority Control Register 26173Register 7-43: IPC27: Interrupt Priority Control Register 27174Register 7-44: IPC28: Interrupt Priority Control Register 28175Register 7-45: IPC29: Interrupt Priority Control Register 29176Register 7-46: INTTREG: Interrupt Control and Status Register1777.4 Interrupt Setup Procedures1787.4.1 Initialization1787.4.2 Interrupt Service Routine1787.4.3 Trap Service Routine1787.4.4 Interrupt Disable1788.0 Direct Memory Access (DMA)179TABLE 8-1: DMA Controller Channel to Peripheral Associations1798.1 DMAC Registers180FIGURE 8-1: Top Level System Architecture Using a Dedicated Transaction Bus180Register 8-1: DMAxCON: DMA Channel x Control Register181Register 8-2: DMAxREQ: DMA Channel x IRQ Select Register182Register 8-3: DMAxSTA: DMA Channel x RAM Start Address Offset Register A182Register 8-4: DMAxSTB: DMA Channel x RAM Start Address Offset Register B183Register 8-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)183Register 8-6: DMAxCNT: DMA Channel x Transfer Count Register(1)184Register 8-7: DMACS0: DMA Controller Status Register 0185Register 8-8: DMACS1: DMA Controller Status Register 1186Register 8-9: DSADR: Most Recent DMA RAM Address Register1879.0 Oscillator Configuration189FIGURE 9-1: Oscillator System Diagram1909.1 CPU Clocking System1919.1.1 System Clock sources1919.1.2 System Clock Selection191EQUATION 9-1: Device Operating Frequency191TABLE 9-1: Configuration Bit Values for Clock Selection1919.1.3 PLL Configuration192EQUATION 9-2: Fosc Calculation192EQUATION 9-3: XT with PLL Mode Example192FIGURE 9-2: PLL Block Diagram1929.2 Auxiliary Clock Generation1939.3 Reference Clock Generation1939.4 Oscillator Control Registers194Register 9-1: OSCCON: Oscillator Control Register(1)194Register 9-2: CLKDIV: Clock Divisor Register196Register 9-3: PLLFBD: PLL Feedback Divisor Register197Register 9-4: OSCTUN: Oscillator TUNING Register198Register 9-5: aclkcon: auxiliary clock divisor control register199Register 9-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER2009.5 Clock Switching Operation2019.5.1 Enabling Clock Switching2019.5.2 Oscillator Switching Sequence2019.6 Fail-Safe Clock Monitor (FSCM)20110.0 Power-Saving Features20310.1 Clock Frequency and Clock Switching20310.2 Instruction-Based Power-Saving Modes20310.2.1 Sleep Mode203EXAMPLE 10-1: PWRSAV Instruction Syntax20310.2.2 Idle Mode20410.2.3 Interrupts Coincident with Power Save Instructions20410.3 Doze Mode20410.4 PWM Power-Saving Features20410.5 Peripheral Module Disable205Register 10-1: PMD1: Peripheral Module Disable Control Register 1206Register 10-2: PMD2: Peripheral Module Disable Control Register 2208Register 10-3: PMD3: Peripheral Module Disable Control Register 3209Register 10-4: PMD4: Peripheral Module Disable Control Register 4209Register 10-5: PMD6: Peripheral Module Disable Control Register 6210Register 10-6: PMD7: Peripheral Module Disable Control Register 721111.0 I/O Ports21311.1 Parallel I/O (PIO) Ports213FIGURE 11-1: Block Diagram of a Typical Shared Port Structure21411.2 Open-Drain Configuration21511.3 Configuring Analog Port Pins21511.4 I/O Port Write/Read Timing21511.5 Input Change Notification (ICN)215EQUATION 11-1: Port Write/Read Example21512.0 Timer1217TABLE 12-1: Timer Mode Settings217FIGURE 12-1: 16-Bit Timer1 Module Block Diagram217Register 12-1: T1CON: Timer1 Control Register21813.0 Timer2/3/4/5 features219FIGURE 13-1: Type B Timer Block Diagram (x = 2, 4)219FIGURE 13-2: Type C Timer Block Diagram (X = 3, 5)219TABLE 13-1: Timer Mode Settings22013.1 16-Bit Operation22013.2 32-Bit Operation220TABLE 13-2: 32-Bit Timer220FIGURE 13-3: 32-Bit Timer Block Diagram221Register 13-1: TxCON: Timerx Control Register (x = 2, 4)222Register 13-2: TyCON: Timery Control Register (y = 3, 5)22314.0 Input Capture225FIGURE 14-1: Input Capture x Block Diagram22514.1 Input Capture Registers226Register 14-1: ICxCON: Input Capture x Control Register (x = 1 to 4)22615.0 Output Compare227FIGURE 15-1: Output Compare x Module Block Diagram22715.1 Output Compare Modes228TABLE 15-1: Output Compare Modes228FIGURE 15-2: Output Compare x Operation228Register 15-1: OCxCON: Output Compare x Control Register (x = 1 to 4)22916.0 High-Speed PWM23116.1 Features Overview23116.2 Feature Description231FIGURE 16-1: High-speed PWMx Module Architectural diagram232FIGURE 16-2: Simplified Conceptual Block Diagram of the High-Speed PWMx23316.3 Control Registers234Register 16-1: PTCON: PWM Time Base Control Register235Register 16-2: PTCON2: PWM Clock Divider Select Register 2237Register 16-3: PTPER: PWM Primary Master Time Base Period Register(1,2)237Register 16-4: SEVTCMP: PWM Special Event Compare Register(1)238Register 16-5: STCON: PWM Secondary Master Time Base Control Register239Register 16-6: STCON2: PWM Secondary Clock Divider Select Register 2240Register 16-7: STPER: PWM Secondary Master Time Base Period Register240Register 16-8: SSEVTCMP: PWM Secondary Special Event Compare Register241Register 16-9: CHOP: PWM Chop Clock Generator Register(1)241Register 16-10: MDC: PWM Master Duty Cycle Register(1,2)242Register 16-11: PWMCONx: PWM Control x Register243Register 16-12: PDCx: PWM Generator Duty Cycle x Register(1,2,3)245Register 16-13: SDCx: PWM Secondary Duty Cycle x Register(1,2,3)245Register 16-14: PHASEx: PWM Primary Phase-Shift x Register(1,2)246Register 16-15: SPHASEx: PWM Secondary Phase-Shift x Register(1,2)247Register 16-16: DTRx: PWM Dead-Time x Register248Register 16-17: ALTDTRx: PWM Alternate Dead-Time x Register248Register 16-18: TRGCONx: PWM Trigger Control x Register249Register 16-19: IOCONx: PWM I/O Control x Register250Register 16-20: TRIGx: PWM Primary Trigger x Compare Value Register251Register 16-21: FCLCONx: PWM Fault Current-Limit Control x Register252Register 16-22: STRIGx: PWM Secondary Trigger x Compare Value Register(1)254Register 16-23: LEBCONx: Leading-Edge Blanking Control x Register255Register 16-24: LEBDLYx: Leading-Edge Blanking Delay x Register257Register 16-25: AUXCONx: PWM Auxiliary Control x Register258Register 16-26: PWMCAPx: Primary PWM Time Base Capture x Register25917.0 Quadrature Encoder Interface (QEI) Module261FIGURE 17-1: Quadrature Encoder Interface x Block Diagram (x = 1 or 2)261Register 17-1: QEIxCON: QEIx Control Register (x = 1 or 2)262Register 17-2: DFLTxCON: Digital Filter x Control Register26418.0 Serial Peripheral Interface (SPI)265FIGURE 18-1: SPIx Module Block Diagram265Register 18-1: SPIxSTAT: SPIx Status and Control Register266Register 18-2: SPIxCON1: SPIx Control Register 1267Register 18-3: SPIxCON2: SPIx Control Register 226919.0 Inter-Integrated Circuit (I2C™)27119.1 Operating Modes27119.2 I2C Registers271FIGURE 19-1: I2Cx Block Diagram (x = 1 or 2)272Register 19-1: I2CxCON: I2Cx Control Register273Register 19-2: I2CxSTAT: I2Cx Status Register275Register 19-3: I2CxMSK: I2Cx Slave Mode Address Mask Register27720.0 Universal Asynchronous Receiver Transmitter (UART)279FIGURE 20-1: Simplified UARTx Block Diagram279Register 20-1: UxMODE: UARTx Mode Register280Register 20-2: UxSTA: UARTx Status and Control Register28221.0 Enhanced CAN (ECAN™) Module28521.1 Overview28521.2 Frame Types285FIGURE 21-1: ECANx Module Block Diagram28621.3 Modes of Operation28721.3.1 Initialization Mode28721.3.2 Disable Mode28721.3.3 Normal Operation Mode28721.3.4 Listen Only Mode28721.3.5 Listen All Messages Mode28721.3.6 Loopback Mode287Register 21-1: CxCTRL1: ECANx CONTROL REGISTER 1288Register 21-2: CxCTRL2: ECANx Control Register 2289Register 21-3: CxVEC: ECANx Interrupt Code Register290Register 21-4: CxFCTRL: ECANx FIFO Control Register291Register 21-5: CxFIFO: ECANx FIFO Status Register292Register 21-6: CxINTF: ECANx Interrupt Flag Register293Register 21-7: CxINTE: ECANx Interrupt Enable Register295Register 21-8: CxEC: ECANx Transmit/Receive Error Count Register296Register 21-9: CxCFG1: ECANx Baud Rate Configuration Register 1296Register 21-10: CxCFG2: ECANx Baud Rate Configuration Register 2297Register 21-11: CxFEN1: ECANx Acceptance Filter Enable Register 1298Register 21-12: CxBUFPNT1: ECANx Filter 0-3 Buffer Pointer Register 1298Register 21-13: CxBUFPNT2: ECANx Filter 4-7 Buffer Pointer Register 2299Register 21-14: CxBUFPNT3: ECANx Filter 8-11 Buffer Pointer Register 3300Register 21-15: CxBUFPNT4: ECANx Filter 12-15 Buffer Pointer Register 4301Register 21-16: CxRXFnSID: ECANx Acceptance Filter n Standard Identifier Register (n = 0-15)302Register 21-17: CxRXFnEID: ECANx Acceptance Filter n Extended Identifier Register (n = 0-15)303Register 21-18: CxFMSKSEL1: ECANx Filter 7-0 Mask Selection Register 1303Register 21-19: CxFMSKSEL2: ECANx Filter 15-8 Mask Selection Register 2304Register 21-20: CxRXMnSID: ECANx Acceptance Filter Mask n Standard Identifier Register (n = 0-2)305Register 21-21: CxRXMnEID: ECANx Acceptance Filter Mask n Extended Identifier Register (n = 0-2)305Register 21-22: CxRXFUL1: ECANx Receive Buffer Full Register 1306Register 21-23: CxRXFUL2: ECANx Receive Buffer Full Register 2306Register 21-24: CxRXOVF1: ECANx Receive Buffer Overflow Register 1307Register 21-25: CxRXOVF2: ECANx Receive Buffer Overflow Register 2307Register 21-26: CxTRmnCON: ECANx TX/RX Buffer mn Control Register (m = 0, 2, 4, 6; n = 1, 3, 5, 7)30821.4 ECANx Message Buffers30922.0 High-Speed, 10-Bit Analog-to-Digital Converter (ADC)31322.1 Features Overview31322.2 Module Description31322.3 Module Functionality314FIGURE 22-1: ADC Block Diagram for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 Devices with one SAR315FIGURE 22-2: ADC Block Diagram for dsPIC33FJ32GS606 and dsPIC33FJ64GS606 devices with two SARs316FIGURE 22-3: ADC Block Diagram for dsPIC33FJ32GS608 and dsPIC33FJ64GS608 devices with two SARs317FIGURE 22-4: ADC Block Diagram for dsPIC33FJ32GS610 and dsPIC33FJ64GS610 devices with two SARs318Register 22-1: ADCON: ADC Control Register319Register 22-2: ADSTAT: ADC Status Register321Register 22-3: ADBASE: ADC Base Register(1,2)322Register 22-4: ADPCFG: ADC Port Configuration Register323Register 22-5: ADPCFG2: ADC Port Configuration Register 2323Register 22-6: ADCPC0: ADC Convert Pair Control Register 0324Register 22-7: ADCPC1: ADC Convert Pair Control Register 1327Register 22-8: ADCPC2: ADC Convert Pair Control Register 2330Register 22-9: ADCPC3: ADC Convert Pair Control Register 3333Register 22-10: ADCPC4: ADC Convert Pair Control Register 4336Register 22-11: ADCPC5: ADC Convert Pair Control Register 5339Register 22-12: ADCPC6: ADC Convert Pair Control Register 6(2)34223.0 High-Speed Analog Comparator34523.1 Features Overview34523.2 Module Description345FIGURE 23-1: High-Speed Analog Comparator x Module Block Diagram34523.3 Module Applications34623.4 DAC34623.5 Interaction with I/O Buffers34623.6 Digital Logic34623.7 Comparator Input Range34623.8 DAC Output Range34623.9 Comparator Registers346Register 23-1: CMPCONx: Comparator Control x Register347Register 23-2: CMPDACx: Comparator DAC Control x Register34824.0 Special Features34924.1 Configuration Bits349TABLE 24-1: Device Configuration Register Map349TABLE 24-2: dsPIC33F Configuration Bits Description35024.2 On-Chip Voltage Regulator353FIGURE 24-1: Connections for the On-Chip Voltage Regulator(1,2,3)35324.3 Brown-Out Reset (BOR)35324.4 Watchdog Timer (WDT)35324.4.1 Prescaler/Postscaler35324.4.2 Sleep and Idle Modes35424.4.3 Enabling WDT354FIGURE 24-2: WDT Block diagram35424.5 JTAG Interface35524.6 In-Circuit Serial Programming35524.7 In-Circuit Debugger35524.8 Code Protection and CodeGuard™ Security356TABLE 24-3: Code Flash Security Segment Sizes FOR 64-Kbyte Devices356TABLE 24-4: Code Flash Security Segment Sizes FOR 32-Kbyte Devices35625.0 Instruction Set Summary357TABLE 25-1: Symbols used in Opcode Descriptions358TABLE 25-2: Instruction Set OVERVIEW36026.0 Development Support36526.1 MPLAB X Integrated Development Environment Software36526.2 MPLAB XC Compilers36626.3 MPASM Assembler36626.4 MPLINK Object Linker/ MPLIB Object Librarian36626.5 MPLAB Assembler, Linker and Librarian for Various Device Families36626.6 MPLAB X SIM Software Simulator36726.7 MPLAB REAL ICE In-Circuit Emulator System36726.8 MPLAB ICD 3 In-Circuit Debugger System36726.9 PICkit 3 In-Circuit Debugger/ Programmer36726.10 MPLAB PM3 Device Programmer36726.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits36826.12 Third-Party Development Tools36827.0 Electrical Characteristics369Absolute Maximum Ratings(1)36927.1 DC Characteristics370TABLE 27-1: Operating MIPS vs. Voltage370TABLE 27-2: Thermal Operating Conditions370TABLE 27-3: Thermal Packaging Characteristics370TABLE 27-4: DC Temperature and Voltage specifications371TABLE 27-5: DC Characteristics: Operating Current (Idd)372TABLE 27-6: DC Characteristics: Idle Current (Iidle)374TABLE 27-7: DC Characteristics: Power-Down Current (Ipd)375TABLE 27-8: DC Characteristics: doze Current (Idoze)376TABLE 27-9: DC Characteristics: I/O Pin Input Specifications377TABLE 27-10: DC Characteristics: I/O Pin Output Specifications379TABLE 27-11: Electrical Characteristics: Brown-out Reset (BOR)380TABLE 27-12: DC Characteristics: Program Memory381TABLE 27-13: Internal Voltage Regulator Specifications38127.2 AC Characteristics and Timing Parameters382TABLE 27-14: Temperature and Voltage Specifications – AC382FIGURE 27-1: Load Conditions for Device Timing Specifications382TABLE 27-15: Capacitive Loading Requirements on Output Pins382FIGURE 27-2: External Clock Timing383TABLE 27-16: External Clock Timing Requirements383TABLE 27-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)384TABLE 27-18: Auxiliary PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)384TABLE 27-19: AC Characteristics: Internal FRC Accuracy385TABLE 27-20: AC Characteristics: Internal LPRC Accuracy385FIGURE 27-3: I/O Timing Characteristics386TABLE 27-21: I/O Timing Requirements386FIGURE 27-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics387TABLE 27-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements388FIGURE 27-5: Timer1/2/3 External Clock Timing Characteristics389TABLE 27-23: Timer1 External Clock Timing Requirements(1)389TABLE 27-24: Timer2/4 External Clock Timing Requirements390TABLE 27-25: Timer3/5 External Clock Timing Requirements390FIGURE 27-6: Input Capture x (ICx) Timing Characteristics391TABLE 27-26: Input Capture x timing requirements391FIGURE 27-7: Output Compare x (OCx) Module Timing Characteristics391TABLE 27-27: Output Compare x Module timing requirements391FIGURE 27-8: Output Compare x/PWMx Module Timing Characteristics392TABLE 27-28: Simple OCx/PWMx MODE Timing Requirements392FIGURE 27-9: High-Speed PWMx Module Fault Timing Characteristics393FIGURE 27-10: High-Speed PWMx Module Timing Characteristics393TABLE 27-29: High-Speed PWMx Module Timing Requirements393TABLE 27-30: SPIx Maximum Data/Clock Rate Summary394FIGURE 27-11: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS394FIGURE 27-12: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS394TABLE 27-31: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements395FIGURE 27-13: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS396TABLE 27-32: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements396FIGURE 27-14: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS397TABLE 27-33: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements397FIGURE 27-15: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS398TABLE 27-34: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements399FIGURE 27-16: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS400TABLE 27-35: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements401FIGURE 27-17: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS402TABLE 27-36: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements403FIGURE 27-18: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS404TABLE 27-37: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements405FIGURE 27-19: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)406FIGURE 27-20: I2Cx Bus Data Timing Characteristics (Master mode)406TABLE 27-38: I2Cx Bus Data Timing Requirements (Master Mode)407FIGURE 27-21: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)408FIGURE 27-22: I2Cx Bus Data Timing Characteristics (Slave Mode)408TABLE 27-39: I2Cx Bus Data Timing Requirements (Slave Mode)409TABLE 27-40: 10-Bit, High-speed ADC Module Specifications410TABLE 27-41: 10-Bit, High-speed ADC Module Timing Requirements411FIGURE 27-23: Analog-to-Digital Conversion Timing Per Input411TABLE 27-42: Comparator Module Specifications412TABLE 27-43: DAC Module Specifications412TABLE 27-44: DAC Output Buffer Specifications413FIGURE 27-24: QEA/QEB Input Characteristics413TABLE 27-45: Quadrature Decoder Timing Requirements414FIGURE 27-25: QEI Module Index Pulse Timing Characteristics414TABLE 27-46: QEI Index Pulse Timing Requirements415FIGURE 27-26: TimerQ (QEI Module) External Clock Timing Characteristics415TABLE 27-47: QEI Module External Clock Timing Requirements415FIGURE 27-27: ECAN™ Module I/O Timing Characteristics416TABLE 27-48: ECAN™ Module I/O Timing Requirements416TABLE 27-49: DMA Read/Write Timing Requirements41628.0 50 MIPS Electrical Characteristics417Absolute Maximum Ratings(1)41728.1 DC Characteristics418TABLE 28-1: Operating MIPS vs. Voltage418TABLE 28-2: DC Characteristics: Operating Current (Idd)418TABLE 28-3: DC Characteristics: Idle Current (Iidle)419TABLE 28-4: DC Characteristics: doze Current (Idoze)42028.2 AC Characteristics and Timing Parameters421TABLE 28-5: External Clock Timing Requirements42129.0 DC and AC Device Characteristics Graphs423FIGURE 29-1: Voh – 4x Driver Pins423FIGURE 29-2: Voh – 8x Driver Pins423FIGURE 29-3: Voh – 16x Driver Pins423FIGURE 29-4: Vol – 4x Driver Pins424FIGURE 29-5: Vol – 8x Driver Pins424FIGURE 29-6: Vol – 16x Driver Pins424FIGURE 29-7: Typical Ipd Current @ Vdd = 3.3V425FIGURE 29-8: Typical Idd Current @ Vdd = 3.3V425FIGURE 29-9: Typical Iidle Current @ Vdd = 3.3V425FIGURE 29-10: Typical FRC Frequency @ Vdd = 3.3V425FIGURE 29-11: Typical LPRC Frequency @ Vdd = 3.3V426FIGURE 29-12: Typical INTREF @ Vdd = 3.3V42630.0 Packaging Information42730.1 Package Marking Information42730.1 Package Marking Information (Continued)42830.2 Package Details429Appendix A: Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Devices441Appendix B: Revision History442Revision A (March 2009)442Revision B (November 2009)442TABLE B-1: Major Section Updates442Revision C (February 2010)445TABLE B-2: Major Section Updates445Revision D (January 2012)446TABLE B-3: Major Section Updates446Revision E (October 2012)448Revision F (July 2014)448INDEX449The Microchip Web Site457Customer Change Notification Service457Customer Support457Product Identification System459Worldwide Sales and Service462サイズ： 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