データシート目次TABLE 1: PIC32MX1XX General Purpose Family Features2TABLE 2: PIC32MX2XX USB Family Features332-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog11.0 Device Overview19FIGURE 1-1: Block Diagram19TABLE 1-1: Pinout I/O Descriptions202.0 Guidelines for Getting Started with 32-bit MCUs272.1 Basic Connection Requirements272.2 Decoupling Capacitors27FIGURE 2-1: Recommended Minimum Connection282.3 Capacitor on Internal Voltage Regulator (Vcap)282.4 Master Clear (MCLR) Pin28FIGURE 2-2: MCLR Pin Connections282.5 ICSP Pins282.6 JTAG292.7 External Oscillator Pins29FIGURE 2-3: Suggested Oscillator Circuit Placement292.8 Unused I/Os292.9 Sosc Design Recommendation29FIGURE 2-4: Recommended Oscillator Circuit Placement292.10 Typical Application Connection Examples30FIGURE 2-5: Capacitive Touch Sensing With Graphics Application30FIGURE 2-6: Audio Playback Application303.0 CPU313.1 Features31FIGURE 3-1: MIPS32® M4K® Processor Core Block Diagram313.2 Architecture Overview32Table 3-1: MIPS32® M4K® processor core High-Performance Integer Multiply/Divide Unit Latencies and Repeat Rates32Table 3-2: Coprocessor 0 Registers33Table 3-3: MIPS32® M4K® processor core Exception Types343.3 Power Management343.4 EJTAG Debug Support344.0 Memory Organization354.1 PIC32MX1XX/2XX Memory Layout35FIGURE 4-1: Memory Map on Reset for PIC32MX110/210 Devices (4 KB RAM, 16 KB Flash)36FIGURE 4-2: Memory Map on Reset for PIC32MX120/220 Devices (8 KB RAM, 32 KB Flash)37FIGURE 4-3: Memory Map on Reset for PIC32MX130/230 Devices (16 KB RAM, 64 KB Flash)38FIGURE 4-4: Memory Map on Reset for PIC32MX150/250 Devices (32 KB RAM, 128 KB Flash)39FIGURE 4-5: Memory Map on Reset for PIC32MX170/270 Devices (64 KB RAM, 256 KB Flash)404.2 Special Function Registers41TABLE 4-1: Bus Matrix Register Map41TABLE 4-2: Interrupt Register Map (Continued)42TABLE 4-3: Timer1-Timer5 Register Map44TABLE 4-4: Input Capture 1-Input Capture 5 Register Map45TABLE 4-5: Output Compare 1-Output Compare 5 Register Map46TABLE 4-6: I2C1 and I2C2 Register Map47TABLE 4-7: UART1 and UART2 Register Map48Table 4-8: SPI1 and SPI2 Register Map49TABLE 4-9: ADC Register Map (Continued)50TABLE 4-10: DMA Global Register Map52TABLE 4-11: DMA CRC Register Map52TABLE 4-12: DMA Channels 0-3 Register Map (Continued)53TABLE 4-13: Comparator Register Map56TABLE 4-14: Comparator Voltage Reference Register Map56TABLE 4-15: Flash Controller Register Map57TABLE 4-16: System Control Register Map58TABLE 4-17: DEVCFG: Device Configuration Word Summary59TABLE 4-18: Device and Revision ID Summary59TABLE 4-19: PortA Register Map60TABLE 4-20: PORTB Register Map61TABLE 4-21: PORTC Register Map62Table 4-22: Peripheral Pin Select Input Register Map (Continued)63Table 4-23: Peripheral Pin Select Output Register Map65TABLE 4-24: Parallel Master Port Register Map68TABLE 4-25: RTCC Register Map69TABLE 4-26: CTMU Register Map69TABLE 4-27: USB Register Map (Continued)704.3 Control Registers73Register 4-1: BMXCON: Bus Matrix Configuration Register73Register 4-2: BMXDKPBA: Data RAM Kernel Program Base Address Register74Register 4-3: BMXDUDBA: Data RAM User Data Base Address Register75Register 4-4: BMXDUPBA: Data RAM User Program Base Address Register76Register 4-5: BMXDRMSZ: Data RAM Size Register77Register 4-6: BMXPUPBA: Program Flash (PFM) User Program Base Address Register77Register 4-7: BMXPFMSZ: Program Flash (PFM) Size Register78Register 4-8: BMXBOOTSZ: Boot Flash (IFM) Size Register785.0 Flash Program Memory79Register 5-1: NVMCON: Programming Control Register80Register 5-2: NVMKEY: Programming Unlock Register81Register 5-3: NVMADDR: Flash Address Register81Register 5-4: NVMDATA: Flash Program Data Register82Register 5-5: NVMSRCADDR: Source Data Address Register826.0 Resets83FIGURE 6-1: System Reset Block Diagram83Register 6-1: RCON: Reset Control Register84Register 6-2: RSWRST: Software Reset Register857.0 Interrupt Controller87FIGURE 7-1: Interrupt Controller Module Block Diagram87Table 7-1: Interrupt IRQ, Vector and Bit Location88Register 7-1: INTCON: Interrupt Control Register90Register 7-2: INTSTAT: Interrupt Status Register91Register 7-3: IPTMR: Interrupt Proximity Timer Register91Register 7-4: IFSx: Interrupt Flag Status Register92Register 7-5: IECx: Interrupt Enable Control Register92Register 7-6: IPCx: Interrupt Priority Control Register938.0 Oscillator Configuration95FIGURE 8-1: Oscillator Diagram96Register 8-1: OSCCON: Oscillator Control Register97Register 8-2: OSCTUN: FRC Tuning Register100Register 8-3: REFOCON: Reference Oscillator Control Register101Register 8-4: REFOTRIM: Reference Oscillator Trim Register1039.0 Direct Memory Access (DMA) Controller105FIGURE 9-1: DMA Block Diagram105Register 9-1: DMACON: DMA Controller Control Register106Register 9-2: DMASTAT: DMA Status Register107Register 9-3: DMAADDR: DMA Address Register107Register 9-4: DCRCCON: DMA CRC Control Register (Continued)108Register 9-5: DCRCDATA: DMA CRC Data Register110Register 9-6: DCRCXOR: DMA CRCXOR Enable Register110Register 9-7: DCHxCON: DMA Channel ‘x’ Control Register111Register 9-8: DCHxECON: DMA Channel ‘x’ Event Control Register112Register 9-9: DCHxINT: DMA Channel ‘x’ Interrupt Control Register (Continued)113Register 9-10: DCHxSSA: DMA Channel ‘x’ Source Start Address Register115Register 9-11: DCHxDSA: DMA Channel ‘x’ Destination Start Address Register115Register 9-12: DCHxSSIZ: DMA Channel ‘x’ Source Size Register116Register 9-13: DCHxDSIZ: DMA Channel ‘x’ Destination Size Register116Register 9-14: DCHxSPTR: DMA Channel ‘x’ Source Pointer Register117Register 9-15: DCHxDPTR: DMA Channel ‘x’ Destination Pointer Register117Register 9-16: DCHxCSIZ: DMA Channel ‘x’ Cell-Size Register118Register 9-17: DCHxCPTR: DMA Channel ‘x’ Cell Pointer Register118Register 9-18: DCHxDAT: DMA Channel ‘x’ Pattern Data Register11910.0 USB On-The-Go (OTG)121FIGURE 10-1: PIC32MX1XX/2XX Family USB Interface Diagram122Register 10-1: U1OTGIR: USB OTG Interrupt Status Register123Register 10-2: U1OTGIE: USB OTG Interrupt Enable Register124Register 10-3: U1OTGSTAT: USB OTG Status Register125Register 10-4: U1OTGCON: USB OTG Control Register126Register 10-5: U1PWRC: USB Power Control Register127Register 10-6: U1IR: USB Interrupt Register128Register 10-7: U1IE: USB Interrupt Enable Register129Register 10-8: U1EIR: USB Error Interrupt Status Register130Register 10-9: U1EIE: USB Error Interrupt Enable Register132Register 10-10: U1STAT: USB Status Register133Register 10-11: U1CON: USB Control Register134Register 10-12: U1ADDR: USB Address Register136Register 10-13: U1FRML: USB Frame Number Low Register136Register 10-14: U1FRMH: USB Frame Number High Register137Register 10-15: U1TOK: USB Token Register137Register 10-16: U1SOF: USB SOF Threshold Register138Register 10-17: U1BDTP1: USB Buffer Descriptor Table Page 1 Register138Register 10-18: U1BDTP2: USB Buffer Descriptor Table PAGE 2 Register139Register 10-19: U1BDTP3: USB Buffer Descriptor Table PAGE 3 Register139Register 10-20: U1CNFG1: USB Configuration 1 Register140Register 10-21: U1EP0-U1EP15: USB Endpoint Control Register14111.0 I/O Ports143FIGURE 11-1: Block Diagram of a Typical Multiplexed Port Structure14311.1 Parallel I/O (PIO) Ports14411.2 CLR, SET and INV Registers14411.3 Peripheral Pin Select145FIGURE 11-2: Remappable Input Example for U1RX145Table 11-1: Input Pin Selection146FIGURE 11-3: Example of Multiplexing of Remappable Output for RPA0147Table 11-2: Output Pin Selection148Register 11-1: [pin name]R: Peripheral Pin Select Input Register149Register 11-2: RPnR: Peripheral Pin Select Output Register149Register 11-3: CNCONx: Change Notice control for PORTx Register (x = A, B, C)15012.0 Timer115112.1 Additional Supported Features151FIGURE 12-1: Timer1 Block Diagram151Register 12-1: T1CON: Type A Timer Control Register (Continued)15213.0 Timer2/3, Timer4/515513.1 Additional Supported Features155FIGURE 13-1: Timer2-Timer5 Block Diagram (16-bit)155FIGURE 13-2: Timer2/3, Timer4/5 Block Diagram (32-bit)156Register 13-1: TxCON: Type B Timer Control Register15714.0 Input Capture159FIGURE 14-1: Input Capture Block Diagram159Register 14-1: ICxCON: Input Capture ‘x’ Control Register16015.0 Output Compare163FIGURE 15-1: Output Compare Module Block Diagram163Register 15-1: OCxCON: Output Compare ‘x’ Control Register16416.0 Serial Peripheral Interface (SPI)165FIGURE 16-1: SPI Module Block Diagram165Register 16-1: SPIx CON: SPI Control Register (Continued)166Register 16-2: SPIxCON2: SPI Control Register 2169Register 16-3: SPIxSTAT: SPI Status Register17017.0 Inter-Integrated Circuit™ (I2C™)173FIGURE 17-1: I2C™ Block Diagram174Register 17-1: I2CxCON: I2C™ Control Register (Continued)175Register 17-2: I2CxSTAT: I2C™ Status Register17718.0 Universal Asynchronous Receiver Transmitter (UART)179FIGURE 18-1: UART Simplified Block Diagram179Register 18-1: UxMODE: UARTx Mode Register (Continued)180Register 18-2: UxSTA: UARTx Status and Control Register182FIGURE 18-2: UART Reception184FIGURE 18-3: Transmission (8-bit or 9-bit Data)18419.0 Parallel Master Port (PMP)185FIGURE 19-1: PMP Module Pinout and Connections to External Devices185Register 19-1: PMCON: Parallel Port Control Register186Register 19-2: PMMODE: Parallel Port Mode Register188Register 19-3: PMADDR: Parallel Port Address Register190Register 19-4: PMAEN: Parallel Port Pin Enable Register191Register 19-5: PMSTAT: Parallel Port Status Register (Slave modes only)19220.0 Real-Time Clock and Calendar (RTCC)193FIGURE 20-1: RTCC Block Diagram193Register 20-1: RTCCON: RTC Control Register194Register 20-2: RTCALRM: RTC ALARM Control Register (Continued)196Register 20-3: RTCTIME: RTC Time Value Register198Register 20-4: RTCDATE: RTC Date Value Register199Register 20-5: ALRMTIME: Alarm Time Value Register200Register 20-6: ALRMDATE: Alarm Date Value Register20121.0 10-bit Analog-to-Digital Converter (ADC)203FIGURE 21-1: ADC1 Module Block Diagram203FIGURE 21-2: ADC Conversion Clock Period Block Diagram204Register 21-1: AD1CON1: ADC Control Register 1205Register 21-2: AD1CON2: ADC Control Register 2207Register 21-3: AD1CON3: ADC Control Register 3208Register 21-4: AD1CHS: ADC Input Select Register209Register 21-5: AD1CSSL: ADC Input Scan Select Register21022.0 Comparator211FIGURE 22-1: Comparator Block Diagram211Register 22-1: CMxCON: Comparator Control Register212Register 22-2: CMSTAT: Comparator Status Register21323.0 Comparator Voltage Reference (CVref)215FIGURE 23-1: Comparator Voltage Reference Block Diagram215Register 23-1: CVRCON: Comparator Voltage Reference Control Register21624.0 Charge Time Measurement Unit (CTMU)217FIGURE 24-1: CTMU Block Diagram217Register 24-1: CTMUCON: CTMU Control Register21825.0 Power-Saving Features22125.1 Power Saving with CPU Running22125.2 CPU Halted Methods22125.3 Power-Saving Operation22125.4 Peripheral Module Disable223Table 25-1: Peripheral Module Disable Bits and Locations22326.0 Special Features22526.1 Configuration Bits225Register 26-1: DEVCFG0: Device Configuration Word 0226Register 26-2: DEVCFG1: Device Configuration Word 1 (Continued)228Register 26-3: DEVCFG2: Device Configuration Word 2 (Continued)230Register 26-4: DEVCFG3: Device Configuration Word 3232Register 26-5: CFGCON: Configuration Control Register233Register 26-6: DEVID: Device and Revision ID Register23426.2 Watchdog Timer (WDT)235Figure 26-1: Watchdog TIMER and Power-Up Timer Block Diagram235Register 26-7: WDTCON: Watchdog Timer Control Register23626.3 On-Chip Voltage Regulator237Figure 26-2: Connections for the On-Chip Regulator23726.4 Programming and Diagnostics237Figure 26-3: Block Diagram of Programming, Debugging and Trace Ports23727.0 Instruction Set23928.0 Development Support24128.1 MPLAB X Integrated Development Environment Software24128.2 MPLAB XC Compilers24228.3 MPASM Assembler24228.4 MPLINK Object Linker/ MPLIB Object Librarian24228.5 MPLAB Assembler, Linker and Librarian for Various Device Families24228.6 MPLAB X SIM Software Simulator24328.7 MPLAB REAL ICE In-Circuit Emulator System24328.8 MPLAB ICD 3 In-Circuit Debugger System24328.9 PICkit 3 In-Circuit Debugger/ Programmer24328.10 MPLAB PM3 Device Programmer24328.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits24428.12 Third-Party Development Tools24429.0 Electrical Characteristics24529.1 DC Characteristics246Table 29-1: Operating MIPS vs. Voltage246Table 29-2: Thermal Operating Conditions246Table 29-3: Thermal Packaging Characteristics246Table 29-4: DC Temperature and Voltage Specifications247Table 29-5: DC Characteristics: Operating Current (Idd)248Table 29-6: DC Characteristics: Idle Current (Iidle)249Table 29-7: DC Characteristics: Power-Down Current (Ipd)250Table 29-8: DC Characteristics: I/O Pin Input Specifications251TABLE 29-9: DC Characteristics: I/O Pin Output Specifications252Table 29-10: Electrical Characteristics: BOR252Table 29-11: DC Characteristics: Program Memory253Table 29-12: Comparator Specifications254Table 29-13: Internal Voltage Regulator Specifications25429.2 AC Characteristics and Timing Parameters255Figure 29-1: Load Conditions for Device Timing Specifications255Table 29-14: Capacitive Loading Requirements on Output Pins255Figure 29-2: External Clock Timing255Table 29-15: External Clock Timing Requirements256Table 29-16: PLL Clock Timing Specifications257Table 29-17: Internal FRC Accuracy257Table 29-18: Internal LPRC Accuracy257Figure 29-3: I/O Timing Characteristics258Table 29-19: I/O Timing Requirements258Figure 29-4: Power-On Reset Timing Characteristics259Figure 29-5: External Reset Timing Characteristics260Table 29-20: Resets Timing260Figure 29-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics261Table 29-21: Timer1 External Clock Timing Requirements261Table 29-22: Timer2, 3, 4, 5 External Clock Timing Requirements262Figure 29-7: Input Capture (CAPx) Timing Characteristics262Table 29-23: Input Capture Module Timing Requirements262Figure 29-8: Output Compare Module (OCx) Timing Characteristics263Table 29-24: Output Compare Module Timing Requirements263Figure 29-9: OCx/PWM Module Timing Characteristics263Table 29-25: Simple OCx/PWM Mode Timing Requirements263Figure 29-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics264Table 29-26: SPIx Master Mode (CKE = 0) Timing Requirements264Figure 29-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics265Table 29-27: SPIx Module Master Mode (CKE = 1) Timing Requirements265Figure 29-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics266Table 29-28: SPIx Module Slave Mode (CKE = 0) Timing Requirements266Figure 29-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics267Table 29-29: SPIx Module Slave Mode (CKE = 1) Timing Requirements267Figure 29-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)269Figure 29-15: I2Cx Bus Data Timing Characteristics (Master Mode)269Table 29-30: I2Cx Bus Data Timing Requirements (Master Mode)270Figure 29-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)272Figure 29-17: I2Cx Bus Data Timing Characteristics (Slave Mode)272Table 29-31: I2Cx Bus Data Timing Requirements (Slave Mode)273Table 29-32: ADC Module Specifications275Table 29-33: 10-bit Conversion Rate Parameters277Table 29-34: Analog-to-Digital Conversion Timing Requirements278Figure 29-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000)279Figure 29-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)280Figure 29-20: Parallel Slave Port Timing281Table 29-35: Parallel Slave Port Requirements282Figure 29-21: Parallel Master Port Read Timing Diagram282Table 29-36: Parallel Master Port Read Timing Requirements283Figure 29-22: Parallel Master Port Write Timing Diagram283Table 29-37: Parallel Master Port Write Timing Requirements284Table 29-38: OTG Electrical Specifications284TABLE 29-39: CTMU Current Source Specifications285Figure 29-23: EJTAG Timing Characteristics286Table 29-40: EJTAG Timing Requirements28630.0 50 MHz Electrical Characteristics28730.1 DC Characteristics288Table 30-1: Operating MIPS vs. Voltage288Table 30-2: DC Characteristics: Operating Current (Idd)288Table 30-3: DC Characteristics: Idle Current (Iidle)289Table 30-4: DC Characteristics: Power-Down Current (Ipd)289Table 30-5: External Clock Timing Requirements290Table 30-6: SPIx Master Mode (CKE = 0) Timing Requirements290Table 30-7: SPIx Module Master Mode (CKE = 1) Timing Requirements290Table 30-8: SPIx Module Slave Mode (CKE = 0) Timing Requirements291Table 30-9: SPIx Module Slave Mode (CKE = 1) Timing Requirements29131.0 DC and AC Device Characteristics Graphs293FIGURE 31-1: I/O Output Voltage High (Voh)293FIGURE 31-2: I/O Output Voltage Low (Vol)293FIGURE 31-3: Typical Ipd Current @ Vdd = 3.3V294FIGURE 31-4: Typical Idd Current @ Vdd = 3.3V294FIGURE 31-5: Typical Iidle Current @ Vdd = 3.3V294FIGURE 31-6: Typical FRC Frequency @ Vdd = 3.3V295FIGURE 31-7: Typical LPRC Frequency @ Vdd = 3.3V295FIGURE 31-8: Typical CTMU Temperature DIODE Forward Voltage29532.0 Packaging Information29732.1 Package Marking Information29732.1 Package Marking Information (Continued)29832.2 Package Details299Appendix A: Revision History315TABLE A-1: Major Section Updates315TABLE A-2: Major Section Updates317TABLE A-3: Major Section Updates318TABLE A-4: Major Section Updates319TABLE A-5: Major Section Updates (Continued)320INDEX323The Microchip Web Site327Customer Change Notification Service327Customer Support327Product Identification System328Worldwide Sales and Service330サイズ： 5.94MBページ数： 330Language: Englishマニュアルを開く
