Motorola TMS320C6711D マニュアル

目次

• SPRS292A - TMS320C6711D

  1
• features

  1
• Table of Contents

  2
• REVISION HISTORY

  3
• GDP and ZDP BGA packages (bottom view)

  4
• description

  5
• device characteristics

  6
• device compatibility

  7
• functional block and CPU (DSP core) diagram

  8
• CPU (DSP core) description

  9
• memory map summary

  11
• peripheral register descriptions

  12
• signal groups description

  17
• DEVICE CONFIGURATIONS

  20
  • device configurations at device reset

    20
  • DEVCFG register description

    22
• TERMINAL FUNCTIONS

  23
  • Terminal Functions

    24
• development support

  36
  • Software Development Tools:

    36
  • Hardware Development Tools:

    36
• device support

  37
  • device and development-support tool nomenclature

    37
    • TMX

      37
    • TMP

      37
    • TMS

      37
    • TMDX

      37
    • TMDS

      37
  • documentation support

    39
• CPU CSR register description

  40
• cache configuration (CCFG) register description

  42
• interrupt sources and interrupt selector

  43
• EDMA module and EDMA selector

  44
  • ESEL0 Register (0x01A0 FF00)

    45
  • ESEL1 Register (0x01A0 FF04)

    45
  • ESEL3 Register (0x01A0 FF0C)

    45
• PLL and PLL controller

  46
  • PLLCSR Register (0x01B7 C100)

    49
  • PLLM Register (0x01B7 C110)

    50
  • PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers

    51
  • OSCDIV1 Register (0x01B7 C124)

    52
• general-purpose input/output (GPIO)

  53
• power-down mode logic

  54
  • triggering, wake-up, and effects

    54
• power-supply sequencing

  56
  • system-level design considerations

    56
  • power-supply design considerations

    57
• power-supply decoupling

  57
• IEEE 1149.1 JTAG compatibility statement

  58
• EMIF device speed

  59
• EMIF big endian mode correctness

  60
• bootmode

  61
• reset

  61
• absolute maximum ratings over operating case temperature range (unless otherwise noted)†

  62
• recommended operating conditions‡

  62
• electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)

  63
• PARAMETER MEASUREMENT INFORMATION

  64
  • signal transition levels

    64
  • AC transient rise/fall time specifications

    65
  • timing parameters and board routing analysis

    66
• INPUT AND OUTPUT CLOCKS

  68
  • timing requirements for CLKIN†‡§ (see Figure 22)

    68
  • timing requirements for CLKIN†‡§ (see Figure 22)

    68
  • switching characteristics over recommended operating conditions for CLKOUT2†‡ ( see Figure 23)

    69
  • switching characteristics over recommended operating conditions for CLKOUT3†§ (see Figure 24)

    69
  • timing requirements for ECLKIN† (see Figure 25)

    70
  • switching characteristics over recommended operating conditions for ECLKOUT‡§¶ (see Figure 26)

    70
• ASYNCHRONOUS MEMORY TIMING

  71
  • timing requirements for asynchronous memory cycles†‡§ (see Figure 27-Figure 28)

    71
  • switching characteristics over recommended operating conditions for asynchronous memory cycles†‡§ (see Figure 27–Figure 28)

    71
• SYNCHRONOUS-BURST MEMORY TIMING

  74
  • timing requirements for synchronous-burst SRAM cycles† (see Figure 29)

    74
  • switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ ( see Figure 29 and Figure 30)

    74
• SYNCHRONOUS DRAM TIMING

  76
  • timing requirements for synchronous DRAM cycles† (see Figure 31)

    76
  • switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ ( see Figure 31- Figure 37)

    76
• HOLD\/HOLDA\ TIMING

  82
  • timing requirements for the HOLD\/HOLDA\ cycles† (see Figure 38)

    82
  • switching characteristics over recommended operating conditions for the HOLD\/HOLDA\ cycles†‡ ( see Figure 38)

    82
• BUSREQ TIMING

  83
  • switching characteristics over recommended operating conditions for the BUSREQ cycles ( see Figure 39)

    83
• RESET TIMING

  84
  • timing requirements for reset†‡ (see Figure 40)

    84
  • switching characteristics over recommended operating conditions during reset¶ (see Figure 40)

    84
• EXTERNAL INTERRUPT TIMING

  86
  • timing requirements for external interrupts† (see Figure 41)

    86
• HOST-PORT INTERFACE TIMING

  87
  • timing requirements for host-port interface cycles†‡ (see Figure 42, Figure 43, Figure 44, and Figure 45)

    87
  • switching characteristics over recommended operating conditions during host-port interface cycles†‡ ( see Figure 42, Figure 43, Figure 44, and Figure 45)

    88
• MULTICHANNEL BUFFERED SERIAL PORT TIMING

  91
  • timing requirements for McBSP†‡ (see Figure 46)

    91
  • switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 46)

    92
  • timing requirements for FSR when GSYNC = 1 (see Figure 47)

    94
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 48)

    94
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 48)

    95
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 49)

    96
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 49)

    96
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 50)

    97
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 50)

    98
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 51)

    99
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 51)

    99
• TIMER TIMING

  100
  • timing requirements for timer inputs† (see Figure 52)

    100
  • switching characteristics over recommended operating conditions for timer outputs† ( see Figure 52)

    100
• GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING

  101
  • timing requirements for GPIO inputs†‡ (see Figure 53)

    101
  • switching characteristics over recommended operating conditions for GPIO outputs†§ (see Figure 53)

    101
• JTAG TEST-PORT TIMING

  102
  • timing requirements for JTAG test port (see Figure 54)

    102
  • switching characteristics over recommended operating conditions for JTAG test port ( see Figure 54)

    102
• MECHANICAL DATA

  103
  • package thermal resistance characteristics

    103
  • thermal resistance characteristics (S-PBGA package) for GDP

    103
  • thermal resistance characteristics (S-PBGA package) for ZDP

    103
  • packaging information

    103