Intel 82543GC 사용자 설명서

 

 

15

Workaround:  

When using half-duplex mode, program the 82543GC Gigabit Ethernet Controller for a very high collision 
threshold and allow it to retransmit packets that encounter a late collision. Also, if the “early transmit” feature is 
used, configure the device to retransmit packets that encounter underruns.   

Status:  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

 

Problem:  

Accesses to certain flash memory addresses will not succeed because of address conflicts with registers in the 
82543GC device. Example addresses include offsets 2000h or 3000h. This erratum is closely related to erratum 
#18, Packet Buffer Memory Address Conflicts.  

The flash memory interface cannot be used. 

Workaround:  None. 

 

Status:  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

 

Problem:  

Accesses to certain packet buffer memory addresses will not succeed because of address conflicts with 
registers in the 82543GC device. Example addresses include offsets 12000h or 13000h. This erratum is closely 
related to erratum #17, Flash Memory Address Conflicts.  

Software cannot directly access packet buffer memory. Such accesses are typically performed only for 
diagnostic purposes.  

Workaround:  None. 

 

Status:  

Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller. 

 

Problem:  

When the 82543GC Ethernet Controller is transmitting and receiving simultaneously, it is possible that short 
packets will be corrupted before transmission. In systems with a 64-bit, 66 MHz PCI bus, packets up to 148 
bytes can be affected. In systems with a 32-bit and/or 33 MHz bus, packets up to 64 bytes can be affected. In 
both cases, the corrupted data will appear in the last 16 bytes of data. The data corruption occurs before CRC 
calculation. 

Since the CRC is calculated after the problem occurs, corrupted short packets can be transmitted on the wire 
without indication of corruption (except for any protocol checksum embedded in the packet).  

Workaround:  

For systems with a 64-bit, 66 MHz PCI bus, software should pad all packets equal to 148 or less bytes with an 
additional 16 bytes of pad data. The value of the data does not matter, since the data may be “sacrificed” to the 
corruption problem and the protocol stack at the receiving end station will ignore it anyway. For systems with a 
32-bit and/or 33 MHz bus, software should pad the packets up to the Ethernet minimum of 64 bytes (including 
CRC).  

Status:  

Intel resolved this erratum in the A1 stepping of the 82543GC Gigabit Ethernet Controller. 

 

Problem:  

When the size of a received packet comes within a 64-bit word of filling up all the space in the packet buffer 
memory, internal header information may not get updated properly for the packet. Subsequent DMA cycles may 
transfer corrupted data from the packet buffer into the host system memory. The corrupted packets may be of 
random length, frequently exceeding the maximum Ethernet size.