Intel 253668-032US 사용자 설명서
4-42 Vol. 3
PAGING
— The value of the R/W flag of the PML4E.
— The value of the U/S flag of the PML4E.
— The value of the XD flag of the PML4E.
— The values of the PCD and PWT flags of the PML4E.
The following items detail how a processor may use the PML4 cache:
— If the processor has a PML4-cache entry for a linear address, it may use that
— The value of the U/S flag of the PML4E.
— The value of the XD flag of the PML4E.
— The values of the PCD and PWT flags of the PML4E.
The following items detail how a processor may use the PML4 cache:
— If the processor has a PML4-cache entry for a linear address, it may use that
entry when translating the linear address (instead of the PML4E in memory).
— The processor does not create a PML4-cache entry unless the P flag is 1 and
all reserved bits are 0 in the PML4E in memory.
— The processor does not create a PML4-cache entry unless the accessed flag is
1 in the PML4E in memory; before caching a translation, the processor sets
the accessed flag if it is not already 1.
the accessed flag if it is not already 1.
— The processor may create a PML4-cache entry even if there are no transla-
tions for any linear address that might use that entry (e.g., because the P
flags are 0 in all entries in the referenced page-directory-pointer table).
flags are 0 in all entries in the referenced page-directory-pointer table).
— If the processor creates a PML4-cache entry, the processor may retain it
unmodified even if software subsequently modifies the corresponding PML4E
in memory.
in memory.
•
PDPTE cache (IA-32e paging only).
1
Each PDPTE-cache entry is referenced by
an 18-bit value and is used for linear addresses for which bits 47:30 have that
value. The entry contains information from the PML4E and PDPTE used to
translate such linear addresses:
— The physical address from the PDPTE (the address of the page directory).
— The logical-AND of the R/W flags in the PML4E and the PDPTE.
— The logical-AND of the U/S flags in the PML4E and the PDPTE.
— The logical-OR of the XD flags in the PML4E and the PDPTE.
— The values of the PCD and PWT flags of the PDPTE.
The following items detail how a processor may use the PDPTE cache:
— If the processor has a PDPTE-cache entry for a linear address, it may use that
value. The entry contains information from the PML4E and PDPTE used to
translate such linear addresses:
— The physical address from the PDPTE (the address of the page directory).
— The logical-AND of the R/W flags in the PML4E and the PDPTE.
— The logical-AND of the U/S flags in the PML4E and the PDPTE.
— The logical-OR of the XD flags in the PML4E and the PDPTE.
— The values of the PCD and PWT flags of the PDPTE.
The following items detail how a processor may use the PDPTE cache:
— If the processor has a PDPTE-cache entry for a linear address, it may use that
entry when translating the linear address (instead of the PML4E and the
PDPTE in memory).
PDPTE in memory).
— The processor does not create a PDPTE-cache entry unless the P flag is 1 and
the reserved bits are 0 in the PML4E and the PDPTE in memory.
— The processor does not create a PDPTE-cache entry unless the accessed flags
are 1 in the PML4E and the PDPTE in memory; before caching a translation,
the processor sets any accessed flags that are not already 1.
the processor sets any accessed flags that are not already 1.
1. With PAE paging, the PDPTEs are stored in internal, non-architectural registers. The operation of
these registers is described in Section 4.4.1 and differs from that described here.