Mitsubishi Electronics FX3G 사용자 설명서

다운로드
페이지 964
306
FX
3S
/FX
3G
/FX
3GC
/FX
3U
/FX
3UC
 Series
Programming Manual - Basic & Applied Instruction Edition
11 Rotation and Shift Operation – FNC 30 to FNC 39
11.7 FNC 36 – WSFR / Word Shift Right
11.7
FNC 36 – WSFR / Word Shift Right
Outline
This instruction shifts word devices with "n1" data length rightward by "n2" words.
1. Instruction format
2. Set data
*1.
Do not set a negative value to the number of words to be shifted rightward.
3. Applicable devices
S1: This function is supported only in FX
3G
/FX
3GC
/FX
3U
/FX
3UC
 PLCs.
S2: This function is supported only in FX
3U
/FX
3UC
 PLCs.
Explanation of function and operation
1. 16-bit operation (WSFR and WSFRP)
For "n1" word devices starting from 
, "n2" words are shifted rightward ([1] and [2] shown below).
After shift, "n2" words starting from 
 are shifted to "n2" words starting from [
+n1-n2] ([3] shown below).
Operand Type
Description
Data Type
Head device number to be stored to the shift data after rightward shift
16-bit binary
Head word device number storing data to be shifted rightward
16-bit binary
n1
Word data length of the shift data n2 
≤ n1 ≤ 512
16-bit binary
n2
Number of words to be shifted rightward n2 
≤ n1 ≤ 512
*1
16-bit binary
Oper-
and 
Type
Bit Devices
Word Devices
Others
System User
Digit Specification
System User
Special 
Unit
Index
Con-
stant
Real 
Number
Charac-
ter String
Pointer
X Y M T C S D .b KnX KnY KnM KnS T C D
R U \G
V Z Modify K H
E
" "
P
S1
S2
S1
S2
n1
n2
S1
P
FNC 36
WSFR
16-bit Instruction
9 steps
Mnemonic
Operation Condition
Continuous
Operation
Pulse (Single)
Operation
WSFR
WSFRP

Mnemonic
Operation Condition
32-bit Instruction
  S
  D
  S
  D
   
D
   
S
   
D
Command
input
FNC 36
WSFRP
n1
n2
         +2
         +8
         +2
n2 (in the case of "n2=3")
n1 (in the case of "n1=9")
[1]
Overflow (data to
be deleted)
         +1
         +7          +6          +5          +4          +3
         +1
         +8
         +7          +6          +5
         +4          +3          +2          +1
         +8 to          +3 before shift (n2=3)
[3] Copy
[2]
"n2" bits are
shifted rightward
(n2=3).
         +2 to           before shift (n2=3)
Before
execution
After
execution